A new analytical delay and noise model for on-chip RLC interconnect

In this paper, we develop a 2/sup nd/ order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1/sup st/ order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

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