A new analytical delay and noise model for on-chip RLC interconnect
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Yu Cao | Dennis Sylvester | Xuejue Huang | N. Chang | Chenming Hu | C. Hu | D. Sylvester | Xuejue Huang | N. Chang | Yu Cao
[1] Takayasu Sakurai,et al. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .
[2] Andrew B. Kahng,et al. An analytical delay model for RLC interconnects , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[3] Andrew B. Kahng,et al. An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] J.A. Davis,et al. Compact distributed RLC models for multilevel interconnect networks , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
[5] Lei He,et al. An efficient inductance modeling for on-chip interconnects , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).