Multi-processor systems are becoming increasingly important in consumer electronics as well as in industrial applications, such as automotive software. Tasks need to share data across processing unit boundaries, e.g., local variables, triggering the need for a communication fabric. Therefore, multi-processor systems are constituted not only by a mere set of processing units, but also by communication and memory peripherals. These peripherals are shared resources, i.e., multiple independently executing tasks on multiple processing units compete for accessing them. Real-time tasks execute periodically on a processing element and are constituted by sequential superblocks. In this paper, we consider several models to schedule the superblocks and organize accesses to the shared resources within the superblocks. First, superblocks can be executed sequentially, i.e., a superblock is activated as soon as its preceding superblock has finished, or they can be executed according to a static schedule (preassigned time slots). Second, we consider three models to access shared resources: (1) dedicated access model, in which accesses happen only at the beginning and the end of a superblock, (2) general access model, in which accesses could happen anytime during the execution of a superblock, and (3) hybrid access model, which combines the dedicated and general access models. We show the relation between these models with respect to schedulability and provide experimental results that show that the dedicated phases model with sequential superblocks performs best.
[1]
Petru Eles,et al.
Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
,
2007,
RTSS.
[2]
Rolf Ernst,et al.
Reliable performance analysis of a multicore multithreaded system-on-chip
,
2008,
CODES+ISSS '08.
[3]
Lui Sha,et al.
Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems
,
2008,
2008 Real-Time Systems Symposium.
[4]
Rolf Ernst,et al.
Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources
,
2009,
2009 Design, Automation & Test in Europe Conference & Exhibition.
[5]
Jan Reineke,et al.
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
,
2009,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.