New methods of improving parallel fault simulation in synchronous sequential circuits

In [1]-[2], a highly successy%l parallel fault simulator, called PROOFS, for synchronous sequential circuits has been reported. The performance of PROOFS has been substantially improved in HOPE [3]. In HOPE, a systematic way of screening out faults with short propagation zone is proposed. In this paper, we propose several new techniques which further reduce the fault simulation titi of HOPE. The new techniques are: 1) fictional fault injection, 2) static fault ordering by fanout free regions and 3) dynamic fault ordering of potentially detected faults. The three methods are incorporated into HOPE, called HOPE1.1. HOPEI. 1 shows sign~icant improvement in performance for all the benchmark circuits experimented as compared to HOPE. Experimental results show that HOPEI. 1 is especially effective for large circuits. For s35932 which is the largest circuit experimented, the number of events is reduced by 24% and the CPU time by 53% compared to HOPE.