Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs

[1]  X. Garros,et al.  FDSOI devices with thin BOX and ground plane integration for 32nm node and below , 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

[2]  Direct comparison of Si/High-K and Si/SiO2 channels in advanced FD SOI MOSFETs , 2008, 2008 IEEE International SOI Conference.

[3]  M. Cassé,et al.  The influence of Coulomb centers located in HfO2/SiO2 gate stacks on the effective electron mobility , 2008 .

[4]  T. Skotnicki,et al.  Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance , 2008, IEEE Transactions on Electron Devices.

[5]  G. Eneman,et al.  Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study , 2007, IEEE Transactions on Electron Devices.

[6]  G. Ghibaudo,et al.  Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling , 2006, 2006 International Electron Devices Meeting.

[7]  M. Mouis,et al.  Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters , 2006, IEEE Transactions on Electron Devices.

[8]  V. Fiori,et al.  Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[9]  S. Satoh,et al.  A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[10]  S. Orain,et al.  Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[11]  G. Ghibaudo,et al.  Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs , 2004, IEEE Electron Device Letters.

[12]  Frederic Allibert,et al.  Germanium-on-insulator (GeOI) structures realized by the Smart Cut technology , 2004 .

[13]  Shinichi Takagi,et al.  Experimental Evidence of Inversion-Layer Mobility Lowering in Ultrathin Gate Oxide Metal-Oxide-Semiconductor Field-Effect-Transistors with Direct Tunneling Current , 2002 .

[14]  Sorin Cristoloveanu,et al.  Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture , 2002 .

[15]  Gerard Ghibaudo,et al.  New ratio method for effective channel length and threshold voltage extraction in MOS transistors , 2001 .

[16]  J. Wortman,et al.  Estimation of the effects of remote charge scattering on electron mobility of n-MOSFETs with ultrathin gate oxides , 2000 .

[17]  K. Maex,et al.  Silicide induced pattern density and orientation dependent transconductance in MOS transistors , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[18]  Chenming Hu,et al.  A folded-channel MOSFET for deep-sub-tenth micron era , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[19]  M. Mouis,et al.  Two-dimensional modeling of the enhanced diffusion in thin base n-p-n bipolar transistors after lateral ion implantations , 1995 .

[20]  Y. Taur,et al.  A new 'shift and ratio' method for MOSFET channel-length extraction , 1992, IEEE Electron Device Letters.

[21]  Gerard Ghibaudo,et al.  New method for the extraction of MOSFET parameters , 1988 .

[22]  J.D. Plummer,et al.  Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces , 1980, IEEE Transactions on Electron Devices.

[23]  T. H. Ning,et al.  The scattering of electrons by surface oxide charges and by lattice vibrations at the silicon-silicon dioxide interface , 1972 .

[24]  N. Sclar Neutral Impurity Scattering in Semiconductors , 1956 .