Introduction Static leakage management appears as a major roadblock in device design for the 45nm node. Indeed, the usual device “scaling rule” imposes a SiON gate oxide thickness responsible for a too high leakage in General Purpose (GP) or Low Power (LP) applications. A first solution is the use of High-K dielectrics. Nevertheless, their lack of compatibility with poly-Si gates imposes the use of dual-metal gates [1], requiring new materials or buried conduction channel [2-3], leading to strong DIBL. A first alternative is to minimize the scaling of gate oxide as proposed in [4] by keeping either Poly-Si gate or Single Metal Gate. In the first case, the subsequent loss on device speed performance is evaluated to 20% (Fig.1). Therefore, smart optimisation of device must be performed in order to compensate this speed degradation due to the static leakage reduction. Nevertheless, this conventional “Bulk” option is compatible with consumer electronics applications where a very low-cost is a major driver. The second choice implies using a mid-gap (or close to mid-gap) metal gate in combination with a fully depleted thin-film channel. This ensures the adjustment of threshold voltage for both GP and LP applications and allows a better scaling of total gate capacitance, by suppression of polydepletion effects. A major point in this approach is the cointegration of regular bulk devices, in order to ensure a full compatibility of the I/O platform. The “Silicon On Nothing” (SON) architecture is a promising candidate in this perspective, defining a “Bulk+” architecture. In this paper we show examples of conventional “Bulk” optimisation using Strain-Silicon, advanced USJ and “Bulk+” integration for 45nm node.