A novel variation insensitive clock distribution methodology
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[1] Yu Cao,et al. New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[2] D. Cheng. Field and wave electromagnetics , 1983 .
[3] M.P. Li. Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond , 2009, IEEE Transactions on Advanced Packaging.
[4] Yehea Ismail,et al. On-Chip Inductance in High Speed Integrated Circuits , 2001 .
[5] Yehea I. Ismail,et al. Accurate analytical delay modeling of CMOS clock buffers considering power supply variations , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[6] Jeong-A Lee,et al. High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption , 2004, Asia-Pacific Computer Systems Architecture Conference.