March iC-: an improved version of March C- for ADOFs detection

This paper presents a new March test solution for detection of ADOFs (Address Decoder Open Faults), and resistive-ADOFs that are the consequence of resistive-open defects in address decoders of SRAM memories. In this study, we briefly analyze the test conditions and the March test requirements for these particular faults and we introduce some modifications to the well known March C- making it able to detect ADOFs and resistive-ADOFs, without increasing its complexity and its ability to detect the former target faults. The reformulation of March C-, called March iC-, is essentially based on introducing a particular address sequence and a particular read/write data sequence. The proposed March iC- extends the ability of March-based test solutions in detecting dynamic faults in SRAM memories.

[1]  S. Pravossoudovitch,et al.  Defect-oriented dynamic fault models for embedded-SRAMs , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

[2]  Manoj Sachdev.  Open Defects in CMOS RAM Address Decoders , 1997, IEEE Des. Test Comput..

[3]  Michael Nicolaidis,et al.  Theory of Transparent BIST for RAMs , 1996, IEEE Trans. Computers.

[4]  Ad J. van de Goor,et al.  Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[5]  R. Schaller,et al.  Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).

[6]  Sungju Park,et al.  A microcode-based memory BIST implementing modified march algorithm , 2001, Proceedings 10th Asian Test Symposium.

[7]  J. Otterstedt,et al.  Integration of non-classical faults in standard March tests , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[8]  Marian Marinescu,et al.  Simple and Efficient Algorithms for Functional RAM Testing , 1982, ITC.

[9]  T. W. Williams,et al.  Detection of CMOS address decoder open faults with March and pseudo random memory tests , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[10]  Arnaud Virazel,et al.  March Tests Improvements for Address Decoder Open and Resistive Open Fault Detection , 2004 .

[11]  Arnaud Virazel,et al.  Comparison of open and resistive-open defect test conditions in SRAM address decoders , 2003, 2003 Test Symposium.

[12]  Manoj Sachdev.  Test and testability techniques for open defects in RAM address decoders , 1996, Proceedings ED&TC European Design and Test Conference.

[13]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[14]  Zaid Al-Ars,et al.  Functional memory faults: a formal notation and a taxonomy , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[15]  Emil Gizdarski.  Detection of Delay Faults in Memory Address Decoders , 2000, J. Electron. Test..

[16]  Ad J. van de Goor,et al.  Tests for resistive and capacitive defects in address decoders , 2001, Proceedings 10th Asian Test Symposium.