A reconfigurable 8 GOP ASIC architecture for high-speed data communications

A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated, and synthesized. The proposed architecture compares favorably to classical DSP and FPGA solutions. It differs from general-purpose reconfigurable computing (RC) platforms by emphasizing high-speed application-specific computations over general-purpose flexibility. The proposed architecture can he used to realize any one of several functional blocks needed for the physical layer implementation of data communication systems operating at symbol rates in excess of 125 Msymbols/s. Multiple instances of a chip based on this architecture, each operating in a different mode, can be used to realize the entire physical layer of high-speed data communication systems. The architecture features the following modes (functions): real and complex FIR/IIR filtering, least mean square (LMS)-based adaptive filtering, discrete Fourier transforms (DFT), and direct digital frequency synthesis (DDFS) at up to 125 Msamples/s. All of the modes are mapped onto a common, regular data path with minimal configuration logic and routing. Multiple chips operating in the same mode can be cascaded to allow for larger blocks.

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