论文信息 - Efficient IC design of SC decimation filters

Efficient IC design of SC decimation filters

This paper presents the design steps considered in the development of an integrated circuit for a switched-capacitor decimation filter, for practical application in telecommunication systems, for a sampling rate reduction from 48.20 MHz to 16.07 MHz. The design consists of dimensioning the operational amplifiers, capacitances and analog switches, using a supply voltage of 5 V for a 0.8 /spl mu/m AMS process. Also shown are electrical simulations using SPECTRE and layout detail design. The filter dissipates approximately 46 mW (including the output buffer) at 5 V, and presents a flat frequency response within 0.12 dB from dc to 3.56 MHz.

J.E. Franca | A. Petraglia | F.A.P. Baruqui | S.K. Mitra

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