Formal design and verification methods for shared memory systems

Many modern hardware and software systems axe designed as a collection of components that run concurrently in order to achieve higher performance. These components employ sophisticated protocols for coordinating their actions. The correctness of these protocols is critical for the overall correctness of the system. Traditional debugging techniques such as simulation are increasingly unable to cover all aspects of the protocols. As a result, formal methods, especially model checkers that examine all possible scheduling of the events in the protocol, have gained considerable attention both from academia and industry. This dissertation shows how formal methods can be tailored to a particular domain to address concerns specific to the domain, and in doing so obtain algorithms that perform better on the protocols that occur in the narrower domain. The domain chosen is shared memory system design and verification. The contributions of the dissertation are: (1) a partial order reduction algorithm, called two phase, to improve the effectiveness of the model checkers, (2) a refinement procedure that synthesizes detailed distributed shared memory protocols from high-level specifications, and (3) a testing based approach, called test model checking , that can be used to verify if a given shared memory system correctly implements a given formal memory model. The two phase algorithm is more effective than the current partial order reduction algorithms on a number of protocols, including the protocols that occur in shared memory design. The refinement technique shows how formal methods can exploit domain specific knowledge to support a high-level specification and validation of protocols followed by an automatic synthesis of a detailed implementation. The test model checking approach shows how limitations of model checking can be overcome by combining model checking with traditional testing methods.