A Stepwise Dimension Reduction Approach to Evolutionary Design of Relative Large Combinational Logic Circuits

In this paper, a stepwise dimension reduction (SDR) approach to evolutionary design of relatively large combinational logic circuits is proposed. The proposed method divides the whole circuit into several layers. As for a circuit with one output, the number of input combinations is expected to be reduced layer-by-layer. The current layer's outputs are the next layer's inputs. All layers are evolved separately one after another, and assembled to form a final solution. The experimental results of SDR on parities, multipliers and circuits taken from MCNC library are comparable with those of GDD. Especially, the 19-parity circuit can be evolved successfully.

[1]  E. Stomeo,et al.  Generalized Disjunction Decomposition for Evolvable Hardware , 2006, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[2]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[3]  Marco Tomassini,et al.  Towards Evolvable Hardware , 1996, Lecture Notes in Computer Science.

[4]  Julian Francis Miller,et al.  Cartesian genetic programming , 2000, GECCO '10.

[5]  Mehrdad Salami,et al.  Evolvable hardware at function level , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[6]  Jim Tørresen,et al.  A Divide-and-Conquer Approach to Evolvable Hardware , 1998, ICES.

[7]  John R. Koza,et al.  Genetic programming - on the programming of computers by means of natural selection , 1993, Complex adaptive systems.

[8]  Tatiana Kalganova,et al.  A Novel Genetic Algorithm for Evolvable Hardware , 2006, 2006 IEEE International Conference on Evolutionary Computation.

[9]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[10]  Xin Yao,et al.  Using Negative Correlation to Evolve Fault-Tolerant Circuits , 2003, ICES.

[11]  Julian Francis Miller,et al.  Scalability problems of digital circuit evolution evolvability and efficient designs , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[12]  Aloysio Pedroza,et al.  Using Genetic Programming and High Level Synthesis to Design Optimized Datapath , 2003, ICES.

[13]  Hitoshi Iba,et al.  Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems , 1995, Towards Evolvable Hardware.

[14]  Julian Francis Miller,et al.  Principles in the Evolutionary Design of Digital Circuits—Part II , 2000, Genetic Programming and Evolvable Machines.

[15]  Tatiana Kalganova,et al.  On evolution of relatively large combinational logic circuits , 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

[16]  Peter J. Bentley,et al.  Development brings scalability to hardware evolution , 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

[17]  Mehrdad Salami,et al.  Evolvable Hardware Chip for High Precision Printer Image Compression , 1998, AAAI/IAAI.

[18]  Tatiana Kalganova,et al.  Bidirectional incremental evolution in extrinsic evolvable hardware , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[19]  David E. Goldberg,et al.  The compact genetic algorithm , 1999, IEEE Trans. Evol. Comput..

[20]  Lukás Sekanina,et al.  Evolutionary Design of Digital Circuits: Where Are Current Limits? , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[21]  Sanyou Zeng,et al.  Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings , 2007, ICES.