A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz

A frequency-translating ΔΣ ADC is fabricated in 1V 65nm CMOS for use in digital-IF receivers. Its bandpass ΔΣ architecture uses single-path mixing inside the ΔΣ loop to downconvert a 4MHz input band from 225MHz (IF<inf>1</inf>) to 25MHz (IF<inf>2</inf>). It achieves an SNDR of 55dB, while consuming only 13mW. This low power is realized by sampling at a frequency lower than IF<inf>1</inf>, and by noise-shaping primarily at IF<inf>2</inf>.

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