Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs

In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowering, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire FinFETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.

[1]  U. Chung,et al.  Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[2]  M. Ancona,et al.  Macroscopic physics of the silicon inversion layer. , 1987, Physical review. B, Condensed matter.

[3]  J. Plummer,et al.  Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's , 1997, IEEE Electron Device Letters.

[4]  T. J. Walls,et al.  Quantum mechanical modeling of advanced sub-10 nm MOSFETs , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

[5]  Jong-Tea Park,et al.  Pi-Gate SOI MOSFET , 2001, IEEE Electron Device Letters.

[6]  S. Datta,et al.  Silicon nano-transistors and breaking the 10 nm physical gate length barrier , 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

[7]  T. Hiramoto,et al.  Impact of quantum mechanical effects on design of nano-scale narrow channel n- and p-type MOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[8]  Yiming Li,et al.  A Two-Dimensional Quantum Transport Simulation of Nanoscale Double-Gate MOSFETs Using Parallel Adaptive Technique , 2004, IEICE Trans. Inf. Syst..

[9]  Yiming Li,et al.  A parallel monotone iterative method for the numerical solution of multi-dimensional semiconductor Poisson equation , 2003 .

[10]  Y. Naveh,et al.  Modeling of 10-nm-scale ballistic MOSFET's , 2000, IEEE Electron Device Letters.

[11]  Mario G. Ancona,et al.  Equations of state for silicon inversion layers , 2000 .

[12]  H. Min,et al.  A numerically efficient method for the hydrodynamic density-gradient model , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

[13]  J. Bokor,et al.  Sensitivity of double-gate and FinFETDevices to process variations , 2003 .

[14]  Y. Yeo,et al.  25 nm CMOS Omega FETs , 2002, Digest. International Electron Devices Meeting,.

[15]  M. Mendicino,et al.  Integration challenges of new materials and device architectures for IC applications , 2004, 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).

[16]  Z. Ren,et al.  A numerical study of ballistic transport in a nanoscale MOSFET , 2002 .

[17]  S. Selberherr,et al.  Comparison of numerical quantum device models , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

[18]  T. Skotnicki,et al.  50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[19]  Andrew R. Brown,et al.  Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study , 2001 .

[20]  T. Toyabe.  Two and three dimensional MOSFETs simulation with density gradient model , 2004, The Fourth International Workshop on Junction Technology, 2004. IWJT '04..

[21]  Yiming Li,et al.  Modeling of quantum effects for ultrathin oxide MOS structures with an effective potential , 2002 .

[22]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[23]  S. Datta.  Electrical resistance: an atomistic view , 2004, cond-mat/0408319.

[24]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[25]  Toshitsugu Sakamoto,et al.  Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors , 2000 .

[26]  Massimo V. Fischetti,et al.  Scaling MOSFETs to the Limit: A Physicists's Perspective , 2003 .

[27]  N. Sano,et al.  Device modeling and simulations toward sub-10 nm semiconductor devices , 2002 .

[28]  S. Datta,et al.  Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches , 2002 .

[29]  Andrew R. Brown,et al.  The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices , 2002 .

[30]  W. Fichtner,et al.  Quantum device-simulation with the density-gradient model on unstructured grids , 2001 .

[31]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs , 2004 .

[32]  T. J. Walls,et al.  Nanoscale silicon MOSFETs: A theoretical study , 2003 .

[33]  Shigeyoshi Watanabe.  Impact of three-dimensional transistor on the pattern area reduction for ULSI , 2003 .

[34]  Can the Density Gradient Approach Describe the Source-Drain Tunnelling in Decanano Double-Gate MOSFETs? , 2002 .

[35]  M. Anantram,et al.  Role of scattering in nanotransistors , 2002, cond-mat/0211069.

[36]  Yiming Li,et al.  A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation , 2002, Engineering with Computers.

[37]  PMOS body-tied FinFET (Omega MOSFET) characteristics , 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

[38]  Shinji Odanaka,et al.  Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[39]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs: device design guidelines , 2002 .

[40]  M. Ogawa,et al.  Quantum transport modeling in nano-scale devices , 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.

[41]  Mark S. Lundstrom,et al.  Quantum mechanical analysis of channel access geometry and series resistance in nanoscale transistors , 2004 .

[42]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[43]  T. J. Walls,et al.  MOSFETs below 10 nm: quantum theory , 2003 .

[44]  Siegfried Selberherr,et al.  A Monte Carlo Method Seamlessly Linking Quantum and Classical Transport Calculations , 2003 .

[45]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[46]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[47]  Andrew R. Brown,et al.  Simulation of direct source-to-drain tunnelling using the density gradient formalism: Non-Equilibrium Greens Function calibration , 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.

[48]  Chenming Hu,et al.  5nm-gate nanowire FinFET , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[49]  Shao-Ming Yu,et al.  A unified quantum correction model for nanoscale single- and double-gate MOSFETs under inversion conditions , 2004 .

[50]  B. Sorée,et al.  Quantum transport in a cylindrical sub-0.1 μm silicon-based MOSFET , 2002 .

[51]  Efficient quantum three-dimensional modeling of fully depleted ballistic silicon-on-insulator metal-oxide-semiconductor field-effect-transistors , 2004 .

[52]  A. Ogura,et al.  Sub-10-nm planar-bulk-CMOS devices using lateral junction control , 2003, IEEE International Electron Devices Meeting 2003.

[53]  D. Ferry.  The onset of quantization in ultra-submicron semiconductor devices , 2000 .

[54]  M. Lundstrom,et al.  Does source-to-drain tunneling limit the ultimate scaling of MOSFETs? , 2002, Digest. International Electron Devices Meeting,.

[55]  T. Chao,et al.  Numerical simulation of quantum effects in high-k gate dielectric MOS structures using quantum mechanical models , 2002 .

[56]  J. Kavalieros,et al.  High performance fully-depleted tri-gate CMOS transistors , 2003, IEEE Electron Device Letters.

[57]  Ting-wei Tang,et al.  Discretization Scheme for the Density-Gradient Equation and Effect of Boundary Conditions , 2002 .

[58]  Andrew R. Brown,et al.  Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter , 2002 .

[59]  S. Selberherr,et al.  Technology CAD: Device simulation and characterization , 2002 .