Caching and Prefetching Policies Using Program Page Reference Patterns on a File System Layer for NAND Flash Memory

Caching and prefetching policies have been used in most of computer systems to compensate speed differences between primary memory and secondary storage devices. In this paper, we design and implement a Flash Cache Core Module(FCCM) on the YAFFS which operates on a file system layer for NAND flash memory. The FCCM is independent of the underlying kernel in order to support its stability and compatibility. Also, we implement the Dirty-Last memory replacement technique considering the characteristics of flash memory, and the waiting queue for pages to be prefetched according to page hit. The FCCM reduced the number of I/Os and the amount of prefetched pages by maximum 55%(20% on average) and maximum 55%(24% on average), respectively, comparing with caching and prefetching policies of Linux.

[1]  K. Korner,et al.  Intelligent caching for remote file service , 1990, Proceedings.,10th International Conference on Distributed Computing Systems.

[2]  Alan Jay Smith,et al.  Sequential Program Prefetching in Memory Hierarchies , 1978, Computer.

[3]  Jin-Soo Kim,et al.  FAB: flash-aware buffer management policy for portable media players , 2006, IEEE Transactions on Consumer Electronics.

[4]  Christos Faloutsos,et al.  Flexible and Adaptable Buffer Management Techniques for Database Management Systems , 1995, IEEE Trans. Computers.

[5]  Pei Cao,et al.  Adaptive page replacement based on memory reference behavior , 1997, SIGMETRICS '97.

[6]  Dan Duchamp,et al.  Detection and exploitation of file working sets , 1991, [1991] Proceedings. 11th International Conference on Distributed Computing Systems.

[7]  Sang Lyul Min,et al.  Design, Implementation, and Performance Evaluation of a Detection-Based Adaptive Block Replacement Scheme , 2002, IEEE Trans. Computers.

[8]  Chanik Park,et al.  Energy-aware demand paging on NAND flash-based embedded storages , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).