论文信息 - 4.2 Gbits/sec Single-chip Fpga Implementation of the Aes Algorithm

4.2 Gbits/sec Single-chip Fpga Implementation of the Aes Algorithm

This letter presents a high performance encryptor/decryptor core of the Advanced Encryption Standard (AES). The proposed architecture is implemented on a single-chip-FPGA using a fully pipelined approach. The results obtained show that our design offers up to 25.06% less area and yields up to 27.23% higher throughput than the fastest AES FPGA implementations reported to date.

F. Rodríguez-Henríquez | N. A. Saqib | A. Díaz-Pérez

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