Optimization criteria for SRAM design: lithography contribution

Here we discuss the use of well calibrated resist and etch bias models, in conjunction with a fast microlithography aerial image simulator, to predict and 'optimize' the printed shapes through all critical levels in a dense SRAM design. Our key emphasis here is on 'optimization criteria', namely, having achieved good predictability for printability with lithography models, how to use this capability in conjunction of best electrical performance, yield, and density. The key lithography/design optimization issues discussed here are: (1) tightening of gate width variation by reducing spatial curvature in the source and drain regions, (2) achieving sufficient contact areas, (3) maximizing process window for overlay, (4) reducing leakage mechanisms by reducing contributions of stress and strain due to the printed shape of oxide isolation regions, (5) examining topological differences in design during the optimization process, (6) accounting for mask corner rounding, and (7) designing for scalability to smaller dimensions to achieve optical design reusability issues without hardware.

[1]  Avideh Zakhor,et al.  Experimental results on optical proximity correction with variable-threshold resist model , 1997, Advanced Lithography.

[2]  Umezawa,et al.  Mechanical Stress Induced MOSFET Punch-through And Process Optimization For Deep Submicron TEOS-O/sub 3/ Filled STI Device , 1997, 1997 Symposium on VLSI Technology.

[3]  Eytan Barouch,et al.  Vector aerial image with off-axis illumination , 1993, Advanced Lithography.

[4]  Valery Axelrad,et al.  Efficient computational techniques for aerial imaging simulation , 1996, Advanced Lithography.

[5]  Eytan Barouch,et al.  Achieving sub-half-micron i-line manufacturability through automated OPC , 1997, Advanced Lithography.

[6]  Steven A. Orszag,et al.  Derivation and simulation of higher numerical aperture scalar aerial images , 1992 .

[7]  Eytan Barouch,et al.  Model considerations, calibration issues, and metrology methods for resist-bias models , 1999, Advanced Lithography.

[8]  Timothy A. Brunner,et al.  Approximate models for resist processing effects , 1996, Advanced Lithography.

[9]  Jack A. Mandelman,et al.  The use of simulation in semiconductor technology development , 1990 .

[10]  Avideh Zakhor,et al.  Mathematical and CAD framework for proximity correction , 1996, Advanced Lithography.

[11]  Phillip Colella,et al.  Two new methods for simulating photolithography development in 3D , 1996, Advanced Lithography.

[12]  Alexander Starikov.  Use Of A Single Size Square Serif For Variable Print Bias Compensation In Microlithography: Method, Design, And Practice , 1989, Advanced Lithography.

[13]  F. Jones,et al.  RD3D (computer simulation of resist development in three dimensions) , 1981, IEEE Transactions on Electron Devices.

[14]  Joseph G. Garofalo,et al.  Applications of enhanced optical proximity correction models , 1998, Advanced Lithography.

[15]  Eytan Barouch,et al.  OPTIMASK: an OPC algorithm for chrome and phase-shift mask design , 1995, Advanced Lithography.

[16]  Eytan Barouch,et al.  Comprehensive 3-D notching simulator with nonplanar substrates , 1990, Advanced Lithography.

[17]  T. Yang,et al.  Enhancement of lithographic patterns by using serif features , 1991 .

[18]  Charles R. Szmanda,et al.  Simulations of bar printing over a MOSFET device using i-line and deep-UV resists , 1991, Other Conferences.

[19]  Thomas Kailath,et al.  Phase-shifting masks for microlithography: automated design and mask requirements , 1994 .

[20]  Douglas A. Bernard,et al.  Model-based optical proximity correction including effects of photoresist processes , 1997, Advanced Lithography.

[21]  Ki-Ho Baik,et al.  Novel approximate model for resist process , 1998, Advanced Lithography.