An Optimum Design of FFT Multi-Digit Multiplier and Its VLSI Implementation

We designed a VLSI chip of FFT multiplier based on simple Cooly-Tukey FFT using a floating-point representation with optimal data length based on an experimental error analysis. The VLSI implementation using HITACHI CMOS 0.18μm technology can perform multiplication of 25 to 213 digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFT multiplier at an area cost of 9.05mm2 . The hardware FFT multiplier is 35.7 times faster than the software FFT multiplier for multiplication of 221 digit hexadecimal numbers. Advantage of hardware FFT multiplier over software will increase when more sophisticated FFT architectures are applied to the multiplier. Keyword: FFT, multi-digit multiplier, VLSI, error analysis with the imaginary parts of all zeros, u = (0 ... 0am-1 ...a0)r and v = (0 ... 0bm-1 ...b0)r. Let the product of u and v be h = u . v = (c2m-1 ...c0)r, F (.) be an FFT, and F -1(.) be an inverse FFT. Then we have

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