Monte Carlo simulation of substrate enhanced electron injection in split-gate memory cells

In this paper, we use fullband Monte Carlo simulations and gate current measurements to investigate charge injection in split-gate memory cells under negative substrate bias. It is shown that, in the source-side-injection (SSI) regime, the enhancement of the programming efficiency due to the substrate bias is low, unless very low drain and floating-gate biases are considered. In particular, the enhancement of the efficiency is largely reduced if the drain current is kept constant when comparing different substrate biases. Furthermore, it is observed that the carrier injection profile under negative substrate bias is broader than in the SSI regime, and a substantial amount of charge is injected in the spacer region.

[1]  A. Ghetti,et al.  Assessment of accuracy limitations of full band Monte Carlo device simulation , 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

[2]  P. Woerlee,et al.  A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions , 1994 .

[3]  Luca Selmi,et al.  A comparative analysis of substrate current generation mechanisms in tunneling MOS capacitors , 2002 .

[4]  L. Selmi,et al.  Coupled Monte Carlo simulation of Si and SiO/sub 2/ transport in MOS capacitors , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[5]  J. Bude.  Gate current by impact ionization feedback in sub-micron MOSFET technologies , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

[6]  David Esseni,et al.  A better understanding of substrate enhanced gate current in VLSI MOSFET's and flash cells. I. Phenomenological aspects , 1999 .

[7]  W. Lui,et al.  Exact solution of the Schrodinger equation across an arbitrary one‐dimensional piecewise‐linear potential barrier , 1986 .

[8]  Guido Groeseneken,et al.  HIM0S-a high efficiency flash E/sup 2/PROM cell for embedded memory applications , 1993 .

[9]  L. Selmi,et al.  Injection efficiency of CHISEL gate currents in short MOS devices: physical mechanisms, device implications, and sensitivity to technological parameters , 2000 .

[10]  L. Selmi,et al.  Effect of the gap size on the SSI efficiency of split-gate memory cells , 2006, IEEE Transactions on Electron Devices.

[11]  M.R. Pinto,et al.  Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[13]  S. Beckx,et al.  Gate isolation technology for compact poly-CMP embedded flash memories , 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

[14]  L. Selmi,et al.  Cathode Hot Electrons and Anode Hot Holes in Tunneling MOS Capacitors , 2000, 30th European Solid-State Device Research Conference.

[15]  Karl Hess,et al.  Tunneling through ultrathin SiO2 gate oxides from microscopic models , 2001 .

[16]  P. Goarin,et al.  Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations , 2005, IEEE Transactions on Electron Devices.

[17]  Luca Selmi,et al.  A better understanding of substrate enhanced gate current in VLSI MOSFETs and flash cells. II. Physical analysis , 1999 .

[18]  J. Bude.  Secondary electron flash-A high performance, low power flash technology for 0.35μm and below , 1997 .