A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM

A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sensing circuit with a cascode differential amplifier.<<ETX>>

[1]  Douglas D. Smith,et al.  A 12-ns ECL I/O 256 K*1-bit SRAM using a 1- mu m BiCMOS technology , 1988 .

[2]  Bruce A. Wooley,et al.  A 4-ns 4K*1-bit two-port BiCMOS SRAM , 1988 .

[3]  N. Tamba,et al.  An 8ns 256k Bicmos Ram , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[4]  Ashwin H. Shah,et al.  An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability , 1988 .

[5]  S. Hanamura,et al.  A 9 ns 1 Mb CMOS SRAM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[6]  R. A. Kertis,et al.  A 12ns 256k Bicmos Sram , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[7]  Tetsuya Iizuka,et al.  Hot-carrier generation in submicrometer VLSI environment , 1986 .

[8]  Makoto Suzuki,et al.  A 7-ns/350-mW 64-kbit ECL-compatible RAM , 1987 .

[9]  Katsuhiko Sato,et al.  An 8 ns 1 Mb ECL BiCMOS SRAM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[10]  Richard A. Chapman,et al.  An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[11]  Hiep V. Tran,et al.  An 8ns Battery Back-Up Submicron Bicmos 256k Ecl Sram , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.