Noise suppression scheme for giga-scale DRAM with hundreds of I/Os

A new Constant Current Voltage-Down Converter and a new Partially Inverted data BUS Architecture are proposed. The proposed VDC reduces Vdd1/Vss1 noise to less than 20%, and the proposed BUS architecture reduces Vdd1/Vss1 noise to about 1/n using only n-1 bit flag signals.