Ultra-low dropout linear regulator using an SOI MESFET
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With these promising preliminary results, the next phase is to complete a fully integrated design similar to that in [1] on the 150nm SOI CMOS process. Ideally the performance will improve with respect to the transient responses and Ignd since the error amplifier can be optimally designed for the needs of the MESFET LDO.
[1] S.J. Wilk,et al. 45 GHz silicon MESFETs on a 0.15 µm SOI CMOS process , 2009, 2009 IEEE International SOI Conference.
[2] B. Bakkaloglu,et al. A capacitor-free LDO using a FD Si-MESFET pass transistor , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.
[3] Gabriel A. Rincón-Mora,et al. A 5mA 0.6μm CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.