Trends toward on-chip networked microsystems

This survey paper identifies some trends in the application, implementation technology, and processor architecture areas. A taxonomy which captures the influence of these trends on processor microsystems is presented, and the communication needs of various classes of these architectures is also briefly surveyed. We observe a trend toward on-chip networked microsystems derived from logically and physically partitioning the processor architecture. Partitioning the architecture logically enables the parallelism offered by growing application workloads to be well exploited. Partitioning the architecture physically enables the scaling properties of the underlying implementation technology to continue providing increased performance and not be encumbered by chip-crossing wire delay, which no longer is negligible. The impact on future research directions of this paradigm shift in the way microsystems are designed and intraconnected is briefly highlighted.

[1]  Li Shang,et al.  Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links , 2002, IEEE Computer Architecture Letters.

[2]  Anant Agarwal,et al.  Scalar operand networks: on-chip interconnect for ILP in partitioned architectures , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[3]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.

[4]  R. Schaller,et al.  Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).

[5]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[6]  Timothy Mark Pinkston,et al.  A methodology for designing efficient on-chip interconnects on well-behaved communication patterns , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[7]  James E. Smith,et al.  Trace Processors: Moving to Fourth-Generation Microarchitectures , 1997, Computer.

[8]  Antonio María González Colás,et al.  Reducing wire delay penalty through value prediction , 2000, MICRO 2000.

[9]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[10]  José Duato,et al.  Efficient interconnects for clustered microarchitectures , 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

[11]  Jaehyuk Huh,et al.  Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture , 2003, IEEE Micro.

[12]  Richard E. Kessler,et al.  The Alpha 21264 microprocessor , 1999, IEEE Micro.

[13]  José Duato,et al.  Deadlock-Free Dynamic Reconfiguration Schemes for Increased Network Dependability , 2003, IEEE Trans. Parallel Distributed Syst..

[14]  Doug Burger,et al.  An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches , 2002, ASPLOS X.

[15]  David A. Koufaty,et al.  Hyperthreading Technology in the Netburst Microarchitecture , 2003, IEEE Micro.

[16]  Shubhendu S. Mukherjee,et al.  The Alpha 21364 network architecture , 2001, HOT 9 Interconnects. Symposium on High Performance Interconnects.

[17]  Russell Tessier,et al.  ASOC: a scalable, single-chip communications architecture , 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).

[18]  José Duato,et al.  A methodology for developing dynamic network reconfiguration processes , 2003, 2003 International Conference on Parallel Processing, 2003. Proceedings..

[19]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[20]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[21]  Li-Shiuan Peh,et al.  Guest Editorial: Special Section on On-Chip Networks , 2005, IEEE Trans. Parallel Distributed Syst..

[22]  Jian Huang,et al.  The Superthreaded Processor Architecture , 1999, IEEE Trans. Computers.

[23]  Luiz André Barroso,et al.  Piranha: a scalable architecture based on single-chip multiprocessing , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[24]  Mani B. Srivastava,et al.  A survey of techniques for energy efficient on-chip communication , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[25]  W. Dally.  Interconnect-limited VLSI architecture , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[26]  Norman P. Jouppi,et al.  Quantifying the Complexity of Superscalar Processors , 2002 .

[27]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[28]  Norman P. Jouppi,et al.  The multicluster architecture: reducing cycle time through partitioning , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[29]  Trevor N. Mudge,et al.  Power: A First-Class Architectural Design Constraint , 2001, Computer.

[30]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[31]  R. Nagarajan,et al.  A design space evaluation of grid processor architectures , 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

[32]  José Duato,et al.  A theory for deadlock-free dynamic network reconfiguration. Part I , 2005, IEEE Transactions on Parallel and Distributed Systems.

[33]  José Duato,et al.  Fast dynamic reconfiguration in irregular networks , 2000, Proceedings 2000 International Conference on Parallel Processing.

[34]  Shubhendu S. Mukherjee,et al.  The Alpha 21364 Network Architecture , 2002, IEEE Micro.

[35]  Kunle Olukotun,et al.  The Stanford Hydra CMP , 2000, IEEE Micro.

[36]  Balaram Sinharoy,et al.  POWER4 system microarchitecture , 2002, IBM J. Res. Dev..

[37]  Luiz André Barroso,et al.  Web Search for a Planet: The Google Cluster Architecture , 2003, IEEE Micro.

[38]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[39]  Sharad Malik,et al.  Power-driven design of router microarchitectures in on-chip networks , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[40]  Dean M. Tullsen,et al.  Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[41]  Babak Falsafi,et al.  Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor , 2001, ICS '01.

[42]  Manoj Franklin,et al.  Hierarchical interconnects for on-chip clustering , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[43]  Victor V. Zyuban,et al.  Optimization of high-performance superscalar architectures for energy efficiency , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[44]  Synthesis of Packet-Switched Network-on-Chip , 2022 .