ON NON-LINEAR SET ASSOCIATIVE CACHE DESIGN

In the modern world, computer system plays a vital role based on type of applications. Hence, there is a need to research and develop such system to improve its performance. In the field of computer architecture, cache address mapping acts between main memory and cache. Moreover, based on the internal or external request of the system, a bunch of words can be loaded onto cache memory. Due to the volatility nature of internal memory, the cache history gets abscond once the system is deactivated. However, the processor performance is based on various factors such as cache size and hit, write policy, type of cache mapping technique, CPU speed, front side bus, and depth of cache level. For cache, a number of standard cache addresses mapping are available. Among these, some of the well known techniques are set associative, fully associative and direct mapping technique. This paper reviews on non-linear cache address system in quadratic and cubic set associative cache address mapping. The standard set associative mapping is remapped with quadratic set associative technique for to secure the data in a non sequential fashion by having the standard mapping execution time. This work can also be applied to design the cache chip enhancement and improvement.

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