A high-speed, programmable, CSD coefficient FIR filter
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A new high-speed, programmable FIR filter is present, which is a multiplierless filter with CSD encoding coefficients. With this encoding scheme, the speed of filter is improved and the area is optimized. In order to make this filter more applicable, we employ a new programmable CSD encoding structure to make CSD coefficients programmable. In the end of this paper, we design a 10-bits, 18 taps video luminance filter with the filter structure we present. The completed filter core occupies 6.8/spl times/6.8 mmm/sup 2/ of silicon area in Wu-Xi Shanghua 0.6 /spl mu/m 2P2M CMOS technology, and its maximum work frequency is 100 MHz.
[1] H. Samueli,et al. An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients , 1989 .
[2] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..
[3] T. Noguchi,et al. A 15-ns 32*32-b CMOS multiplier with an improved parallel structure , 1990 .
[4] Jun Rim Choi,et al. Structured design of a 288-tap FIR filter by optimized partial product tree compression , 1997 .