An efficient diagnosis methodology for charge pump circuits: Application to flash EEPROM devices

The objective of this paper is to present an efficient diagnosis methodology for charge pump circuits. This method focuses on speeding up the diagnosis process of anomalous variations of charge pump design parameters (transistor widths or pumping capacitance value variation). This methodology is based on a mathematical model generated with a "design of experiment" (DOE) technique. The diagnostic strategy presented in this paper targets EEPROM non volatile memories (NVM) circuits. The diagnosis process begins by measuring threshold voltages values (VT) of an array of EEPROM cells. Then, for anomalous threshold voltages populations, the corresponding high programming voltage HV is evaluated. After that, the diagnosis process is realized by using our mathematical model which links specific charge pump design parameters to the output voltage HV. The final goal is to find root cause of the memory array anomalous VT in terms of charge pump design parameters.

[1]  Angela Arapoyanni,et al.  A CMOS charge pump for low voltage operation , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[2]  David H. Doehlert,et al.  Uniform Shell Designs , 1970 .

[3]  J. F. Dickson,et al.  On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique , 1976 .

[4]  M. Lenzlinger,et al.  Fowler‐Nordheim Tunneling into Thermally Grown SiO2 , 1969 .

[5]  Zhang Fan,et al.  NEW DESIGN OF EEPROM MEMORY FOR RFID TAG IC Embedded EEPROM Memory Achieving Lower Power , 2006 .

[6]  Kazunori Masuda,et al.  A new technique for measuring threshold voltage distribution in flash EEPROM devices , 1995, Proceedings International Conference on Microelectronic Test Structures.

[7]  Romain Laffont,et al.  Decreasing EEPROM programming bias with negative voltage, reliability impact , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[8]  Deng Min,et al.  Embeded EEPROM Memory Achieving Lower Power - New design of EEPROM memory for RFID tag IC , 2006, IEEE Circuits and Devices Magazine.

[9]  Jieh-Tsorng Wu,et al.  MOS charge pumps for low-voltage operation , 1998, IEEE J. Solid State Circuits.