An study of removal of subjective redundancy in JPEG for low cost, low power, computation efficient circuit design and high compression image

As the circuit complexity is increasing in demand for the more computations on a single VLSI chip, low power VLSI design has become important specially for portable devices powered by battery. Digital camera is one of them where realtime image capturing, compression and storage of compressed image data is done. Most of the digital camera implement JPEG baseline algorithm to store highly compressed image in camera memory. In this paper we report and present low cost, low power and computationally efficient circuit design of JPEG for digital camera to get highly compressed image by exploiting removal of subjective redundancy from the image.

[1]  W. B. Mikhael,et al.  Region based variable quantization for JPEG image compression , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[2]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[3]  Antonio Ortega,et al.  A novel approach of image compression in digital cameras with a Bayer color filter array , 2001, Proceedings 2001 International Conference on Image Processing (Cat. No.01CH37205).

[4]  Jar-Ferr Yang,et al.  Direct recursive structures for computing radix-r two-dimensional DCT/IDCT/DST/IDST , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[5]  Gregory K. Wallace,et al.  The JPEG still picture compression standard , 1991, CACM.

[6]  Zhang Xing,et al.  A 250MHz optimized distributed architecture of 2D 8x8 DCT , 2007, 2007 7th International Conference on ASIC.

[7]  S. Kawahito,et al.  A parallel image compression system for high-speed cameras , 2005, IEEE International Workshop on Imaging Systems and Techniques, 2005.

[8]  Saraju P. Mohanty,et al.  VLSI architecture and FPGA prototyping of a digital camera for image security and authentication , 2006, 2006 IEEE Region 5 Conference.

[9]  Mohamed I. Elmasry,et al.  Low-Power Digital VLSI Design: Circuits and Systems , 1995 .

[10]  Zhou Wang,et al.  No-reference perceptual quality assessment of JPEG compressed images , 2002, Proceedings. International Conference on Image Processing.

[11]  Zhang Qihui,et al.  A VLSI implementation of pipelined JPEG encoder for grayscale images , 2009, 2009 International Symposium on Signals, Circuits and Systems.

[12]  K. Venkataraman,et al.  Digital Camera Imaging System Simulation , 2009, IEEE Transactions on Electron Devices.

[13]  D. Mclaren,et al.  Removal of subjective redundancy from DCT-coded images , 1991 .

[14]  Chunyan Wang,et al.  Recursive algorithm, architectures and FPGA implementation of the two-dimensional discrete cosine transform , 2008 .

[15]  Sergio Bampi,et al.  Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs , 2007, Microprocess. Microsystems.

[16]  Nagarajan Ranganathan,et al.  JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard , 1995, Proc. IEEE.

[17]  V. Groza,et al.  Hardware support of JPEG , 2005, Canadian Conference on Electrical and Computer Engineering, 2005..

[18]  Jin-Maun Ho,et al.  The design and test of peripheral circuits of image sensor for a digital camera , 2004, 2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04..