PERFORMANCE ANALYSIS OF HIGHSPEED LOW POWER TG - MULTIPLIERSDESIGNS WITH RADIX-4 MODIFIEDBOOTH RECODING
暂无分享,去创建一个
N. Jayapal | A. Lakshminarayanan | V. Krishnakumar | R. Shankar | M. Dharmalingam | M. Dharmalingam | N. Jayapal | R. Shankar | V. Krishnakumar | A. Lakshminarayanan
[1] Rolf Landauer,et al. Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..
[2] Vojin G. Oklobdzija,et al. A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach , 1996, IEEE Trans. Computers.
[3] S. Hsu,et al. A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS , 2005, IEEE Journal of Solid-State Circuits.
[4] Charles H. Bennett,et al. Logical reversibility of computation , 1973 .
[5] D. H. Jacobsohn,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..
[6] B. Parhami,et al. Fault-Tolerant Reversible Circuits , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.
[7] Guowu Yang,et al. Quantum logic synthesis by symbolic reachability analysis , 2004, Proceedings. 41st Design Automation Conference, 2004..
[8] Pérès,et al. Reversible logic and quantum computers. , 1985, Physical review. A, General physics.
[9] T. Toffoli,et al. Conservative logic , 2002, Collision-Based Computing.
[10] R. Ravi,et al. Optimal Circuits for Parallel Multipliers , 1998, IEEE Trans. Computers.
[11] R. Feynman. Quantum mechanical computers , 1986 .
[12] Milos D. Ercegovac,et al. Digital Arithmetic , 2003, Wiley Encyclopedia of Computer Science and Engineering.
[13] Jean-Luc Gaudiot,et al. A Logarithmic Time Method for Two's Complementation , 2005, International Conference on Computational Science.
[14] O. L. Macsorley. High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.
[15] Jean-Luc Gaudiot,et al. A Simple High-Speed Multiplier Design , 2006, IEEE Transactions on Computers.
[16] Andrew D. Booth,et al. A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .
[17] Tommaso Toffoli,et al. Reversible Computing , 1980, ICALP.
[18] Chein-Wei Jen,et al. High-Speed Booth Encoded Parallel Multiplier Design , 2000, IEEE Trans. Computers.
[19] Robert M. Averill,et al. A radix-8 CMOS S/390 multiplier , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.
[20] Milos D. Ercegovac,et al. High-performance low-power left-to-right array multiplier design , 2005, IEEE Transactions on Computers.
[21] Charles Roth,et al. A low-power, high-speed implementation of a PowerPC/sup TM/ microprocessor vector extension , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).