A 64-Channel Versatile Neural Recording SoC With Activity-Dependent Data Throughput

Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low-noise (2.1 <inline-formula> <tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>V<inline-formula><tex-math notation="LaTeX">$_{\text{rms}}$ </tex-math></inline-formula>), low-power (23 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula>W per analogue channel) neural recording system-on-chip (SoC). This features individually configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth, and sampling rate settings can be independently configured to extract local field potentials at a low data-rate and/or action potentials (APs) at a higher data rate. The sampled data are streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting coprocessor to provide a real-time (low latency) output. The system has been implemented in a commercially available 0.35-<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m CMOS technology occupying a silicon area of 19.1 mm<inline-formula><tex-math notation="LaTeX">$^2$</tex-math></inline-formula> (0.3 mm <inline-formula><tex-math notation="LaTeX">$^2$</tex-math></inline-formula> gross per channel), demonstrating a low-power and efficient architecture that could be further optimized by aggressive technology and supply voltage scaling.