Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling

[1]  Santanu Maity,et al.  RF/Analog performance of GaAs Multi-Fin FinFET with stress effect , 2021, Microelectron. J..

[2]  R. Chaujar,et al.  Numerical Study of JAM-GS-GAA FinFET: A Fin Aspect Ratio Optimization for Upgraded Analog and Intermodulation Distortion Performance , 2021, Silicon.

[3]  V. Narendar,et al.  Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications , 2021, International Journal of RF and Microwave Computer-Aided Engineering.

[4]  V. Narendar,et al.  Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length , 2021, AEU - International Journal of Electronics and Communications.

[5]  Rajesh Saha,et al.  Simulation study on ferroelectric layer thickness dependence RF/Analog and linearity parameters in ferroelectric tunnel junction TFET , 2021, Microelectron. J..

[6]  C. Pandey,et al.  A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET , 2021, Microelectronics Reliability.

[7]  Saleh Mohammadi,et al.  Germanium-source L-shaped TFET with dual in-line tunneling junction , 2021, Applied Physics A.

[8]  V. Narendar,et al.  Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications , 2021, Silicon.

[9]  V. Narendar,et al.  A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length , 2021, Silicon.

[10]  A. Orouji,et al.  Investigation of tied double gate 4H–SiC junctionless FET in 7 nm channel length with a symmetrical dual p+ layer , 2021 .

[11]  N. Gupta,et al.  Assessment of High-k Gate Stack on Sub-10 nm SOI-FinFET for High-Performance Analog and RF Applications Perspective , 2020 .

[12]  Raj Kumar,et al.  Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET) , 2020, Silicon.

[13]  Asisa Kumar Panigrahy,et al.  Performance evaluation of noise coupling on Germanium based TSV filled material for future IC integration technique , 2020 .

[14]  C. Pandey,et al.  Improvement in analog/RF performances of SOI TFET using dielectric pocket , 2020 .

[15]  A. Orouji,et al.  Improvement of Nanoscale SOI MOSFET Heating Effects by Vertical Gaussian Drain-Source Doping Region , 2020, Silicon.

[16]  Yiming Li,et al.  Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps , 2020 .

[17]  Asisa Kumar Panigrahy,et al.  Surface Density Gradient Engineering Precedes Enhanced Diffusion; Drives CMOS In-Line Process Flow Compatible Cu–Cu Thermocompression Bonding at 75 °C , 2019, IEEE Transactions on Device and Materials Reliability.

[18]  S. Baishya,et al.  An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics , 2019, Applied Physics A.

[19]  S. Kale,et al.  Performance Improvement and Analysis of PtSi Schottky Barrier p-MOSFET Based on Charge Plasma Concept for Low Power Applications , 2019, Silicon.

[20]  Seongjae Cho,et al.  Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes , 2018, IEEE Transactions on Electron Devices.

[21]  O. Rozeau,et al.  Performance and design considerations for gate-all-around stacked-NanoWires FETs , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[22]  D. Mocuta,et al.  Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[23]  D. Corliss,et al.  Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET , 2017, 2017 Symposium on VLSI Technology.

[24]  Ram Awadh Mishra,et al.  Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs) , 2015 .

[25]  Diederik Verkest,et al.  Vertical GAAFETs for the Ultimate CMOS Scaling , 2015, IEEE Transactions on Electron Devices.

[26]  K. Roy,et al.  Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs , 2011, IEEE Transactions on Electron Devices.

[27]  O. Faynot,et al.  Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack , 2006, 2006 International Electron Devices Meeting.

[28]  Charles M Lieber,et al.  Semiconductor nanowires , 2006 .

[29]  Narendar Vadthiya,et al.  Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications , 2021 .

[30]  Vadthiya Narendar,et al.  Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes , 2021, Microelectron. J..

[31]  A. Marsh,et al.  The Improvement of , 1952 .