Design Techniques and Architectures for Low-Leakage SRAMs

In high performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for memory devices, for two main reasons. First, memories have historically been designed with performance as the primary figure of merit; therefore, they are intrinsically non power-efficient structures. Second, memories are accessed in small chunks, thus leaving the vast majority of the memory cells unaccessed for a large fraction of the time. In this paper, we present an overview of the techniques proposed both in the academic and in the industrial domain for minimizing leakage power, and in particular, the subthreshold component, in SRAMs. The surveyed solutions range from cell-level techniques to architectural solutions suitable to system-level design.

[1]  Eric Rotenberg,et al.  Adaptive mode control: A static-power-efficient cache design , 2003, TECS.

[2]  Kaushik Roy,et al.  A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Kaushik Roy,et al.  Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  S. Paraneetharan.  Architectural Leakage Power Minimization of Scratchpad memories , 2012 .

[5]  Koji Nii,et al.  A low power SRAM using auto-backgate-controlled MT-CMOS , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[6]  Hiroshi Kawaguchi,et al.  Dynamic leakage cut-off scheme for low-voltage SRAM's , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[7]  Shi-Yu Huang,et al.  X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs , 2008, IEEE Journal of Solid-State Circuits.

[8]  Muhammad M. Khellah,et al.  A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique , 2002, VLSIC 2002.

[9]  M. Khellah,et al.  A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[10]  Koji Nii,et al.  An auto-backgate-controlled MT-CMOS circuit , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[11]  Yuzhuo Fu,et al.  Reducing leakage power in instruction cache using WDC for embedded processors , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[12]  Mahmut T. Kandemir,et al.  Compiler-guided leakage optimization for banked scratch-pad memories , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Manisha Pattanaik,et al.  Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications , 2011 .

[14]  T. Mudge,et al.  Drowsy caches: simple techniques for reducing leakage power , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

[15]  K. Roy,et al.  DRG-cache: a data retention gated-ground cache for low power , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[16]  Frank Vahid,et al.  Low static-power frequent-value data caches , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[17]  Krste Asanovic,et al.  Dynamic fine-grain leakage reduction using leakage-biased bitlines , 2002, ISCA.

[18]  Andreas Moshovos,et al.  Low-leakage asymmetric-cell SRAM , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Kaushik Roy,et al.  Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors , 2002, ISLPED '02.

[20]  Luca Benini,et al.  STV-Cache: a leakage energy-efficient architecture for data caches , 2006, GLSVLSI '06.

[21]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[22]  Ramalingam Sridhar,et al.  NC-SRAM - a low-leakage memory circuit for ultra deep submicron designs , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[23]  Luca Benini,et al.  Specification and analysis of power-managed systems , 2004, Proceedings of the IEEE.

[24]  Margaret Martonosi,et al.  Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.

[25]  Kaushik Roy,et al.  Reducing leakage in a high-performance deep-submicron instruction cache , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[26]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[27]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[28]  Atila Alvandpour,et al.  A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme , 2003 .

[29]  Ching-Te Chuang,et al.  Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors , 2009, IEEE Electron Device Letters.

[30]  Kunihiro Asada,et al.  An architectural level energy reduction technique for deep-submicron cache memories , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[31]  Yong-Bin Kim,et al.  A low leakage 9t sram cell for ultra-low power operation , 2008, GLSVLSI '08.

[32]  Toshinori Sato,et al.  A leakage-energy-reduction technique for highly-associative caches in embedded systems , 2004, SIGARCH Comput. Archit. News.

[33]  K. Itoh,et al.  A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[34]  Tadahiro Kuroda,et al.  A bitline leakage compensation scheme for low-voltage SRAMs , 2001, IEEE J. Solid State Circuits.

[35]  A. Alvandpour,et al.  Bitline leakage equalization for sub-100nm caches , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).