Communication Throughput of Interconnection Networks

Modern flow control techniques used for massively parallel computers have made network capacity a more important parameter for the application performance than network latency. Network latency is usually rather low as long as the injection rate is below a specific value.

[1]  Hee Yong Youn,et al.  Performance analysis of finite buffered multistage interconnection networks , 1992, Proceedings Supercomputing '92.

[2]  Eli Upfal,et al.  A Theory of Wormhole Routing in Parallel Computers , 1996, IEEE Trans. Computers.

[3]  Sanguthevar Rajasekaran,et al.  Optimal routing algorithms for mesh-connected processor arrays , 1988, Algorithmica.

[4]  Nicholas Pippenger,et al.  Parallel Communication with Limited Buffers (Preliminary Version) , 1984, FOCS.

[5]  Ralf Klasing,et al.  Parallel Architectures: Design and Efficient Use , 1993, STACS.

[6]  Eli Upfal,et al.  Efficient schemes for parallel communication , 1982, PODC '82.

[7]  Anant Agarwal,et al.  Limits on Interconnection Network Performance , 1991, IEEE Trans. Parallel Distributed Syst..

[8]  Romas Aleliunas,et al.  Randomized parallel communication (Preliminary Version) , 1982, PODC '82.

[9]  Cauligi S. Raghavendra,et al.  Performance Analysis of a Redundant-Path Interconnection Network , 1985, International Conference on Parallel Processing.

[10]  Leslie G. Valiant,et al.  Universal schemes for parallel communication , 1981, STOC '81.

[11]  Marie-Claude Heydemann,et al.  On forwarding indices of networks , 1989, Discret. Appl. Math..

[12]  Abhiram G. Ranade,et al.  How to emulate shared memory , 1991, 28th Annual Symposium on Foundations of Computer Science (sfcs 1987).

[13]  Debasis Mitra,et al.  Randomized Parallel Communications , 1986, ICPP.

[14]  W. Daniel Hillis,et al.  The Network Architecture of the Connection Machine CM-5 , 1996, J. Parallel Distributed Comput..

[15]  Reinhard Lüling,et al.  A Realizable Efficient Parallel Architecture , 1992, Heinz Nixdorf Symposium.

[16]  Marc Snir,et al.  The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.

[17]  F. Thomson Leighton,et al.  ARRAYS AND TREES , 1992 .

[18]  H. Djidjev On the Problem of Partitioning Planar Graphs , 1982 .

[19]  Ramesh Subramonian,et al.  LogP: towards a realistic model of parallel computation , 1993, PPOPP '93.

[20]  Yih-Chyun Jenq,et al.  Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network , 1983, IEEE J. Sel. Areas Commun..

[21]  Kenneth E. Batcher,et al.  Sorting networks and their applications , 1968, AFIPS Spring Joint Computing Conference.

[22]  John N. Tsitsiklis,et al.  The efficiency of greedy routing in hypercubes and butterflies , 1991, SPAA '91.

[23]  F. Leighton,et al.  Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes , 1991 .

[24]  Juraj Hromkovič,et al.  The Bisection Problem for Graphs of Degree 4 (Configuring Transputer Systems) , 1991, MFCS.

[25]  Bruce M. Maggs,et al.  Simple algorithms for routing on butterfly networks with bounded queues , 1992, STOC '92.

[26]  Frank Thomson Leighton,et al.  Average case analysis of greedy routing algorithms on arrays , 1990, SPAA '90.

[27]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[28]  Reinhard Lüling,et al.  Problem Independent Distributed Simulated Annealing and its Applications , 1993 .

[29]  Jack Dongarra,et al.  Experimental parallel computing architectures , 1987 .

[30]  C. Y. Roger Chen,et al.  Performance analysis of single-buffered multistage interconnection networks , 1991, Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing.

[31]  Joseph JaJa Suggesting computer science agendas for high performance computing: on some technical directions , 1994 .

[32]  Kyungsook Y. Lee,et al.  Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems , 1990, IEEE Trans. Computers.

[33]  R. Entringer,et al.  The bisection width of cubic graphs , 1989, Bulletin of the Australian Mathematical Society.

[34]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[35]  R. Diekmann,et al.  Using helpful sets to improve graph bisections , 1994, Interconnection Networks and Mapping and Scheduling Parallel Computations.

[36]  Erwin P. Rathgeb,et al.  Performance analysis of buffered Banyan networks , 1991, IEEE Trans. Commun..

[37]  B. Monien,et al.  An optimized reconfigurable architecture for transputer networks , 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.

[38]  Jeffrey D Ullma Computational Aspects of VLSI , 1984 .

[39]  W. Daniel Hillis,et al.  The network architecture of the Connection Machine CM-5 (extended abstract) , 1992, SPAA '92.

[40]  R. Tarjan,et al.  A Separator Theorem for Planar Graphs , 1977 .

[41]  Juraj Hromkovic,et al.  The Bisection Problem for Graphs of Degree 4 (Configuring Transputer Systems) , 1992, Informatik.

[42]  Michael Kaufmann,et al.  Derandomizing algorithms for routing and sorting on meshes , 1994, SODA '94.

[43]  A. Klein,et al.  Performance Benefits from Locally Adaptive Interval Routing in Dynamically Switched Interconnection Networks , 1991, EDMCC.

[44]  Leslie G. Valiant,et al.  A Scheme for Fast Parallel Communication , 1982, SIAM J. Comput..

[45]  Fillia Makedon,et al.  A 2n-2 Step Algorithm for Routing in an nxn Array with Constant Size Queues , 1989, SPAA.