Design Of Heterogeneous Ics For Mobile And Personal Communication Systems

Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of flexibility, performance and power dissipation, are driving the development of integrated circuits into the direction of heterogeneous single-chip solutions. New IC architectures are emerging which contain the core of a powerful programmable processor, complemented with dedicated hardware, memory and interface structures. In this tutorial we will discuss the real-life design of a heterogeneous IC for an industrial telecom application: a reconfigurable mobile terminal for satellite communication. Based on this practical design experience, we will subsequently discuss a methodology for the design of heterogeneous ICs. Design steps that will be addressed include: system specification and refinement, data path and communication synthesis, and code generation for embedded processor cores.

[1]  Nikil D. Dutt,et al.  A Representation for the Binding of RT-Component Functionality to HDL Behavior , 1993, CHDL.

[2]  Pierre G. Paulin,et al.  Register assignrnent through resource classification for ASIP microcode generation , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[3]  H. De Man,et al.  Silicon integration of digital user-end mobile communication systems , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[4]  Charles N. Fischer,et al.  Retargetable Compiler Code Generation , 1982, CSUR.

[5]  Takanobu Baba,et al.  The MPG System: A Machine-Independent Efficient Microprogram Generator , 1981, IEEE Transactions on Computers.

[6]  Peter Marwedel,et al.  Tree-based mapping of algorithms to predefined structures , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[7]  S. Ramesh,et al.  Communicating reactive processes , 1993, POPL '93.

[8]  Mani B. Srivastava,et al.  Using VHDL for high-level, mixed-mode system simulation , 1992, IEEE Design & Test of Computers.

[9]  Robert K. Brayton,et al.  Multilevel logic synthesis , 1990, Proc. IEEE.

[10]  Frank Vahid,et al.  System specification and synthesis with the SpecCharts language , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[11]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[12]  Giovanni De Micheli,et al.  Hardware-software cosynthesis for digital systems , 1993, IEEE Design & Test of Computers.

[13]  Amnon Naamad,et al.  Statemate: a working environment for the development of complex reactive systems , 1988, ICSE '88.

[14]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[15]  H. De Man,et al.  Global communication and memory optimizing transformations for low power signal processing systems , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[16]  Gérard Berry,et al.  The Esterel Synchronous Programming Language: Design, Semantics, Implementation , 1992, Sci. Comput. Program..

[17]  Jörg Henkel,et al.  Hardware-software cosynthesis for microcontrollers , 1993, IEEE Design & Test of Computers.

[18]  Hugo De Man,et al.  Cathedral-III : architecture-driven high-level synthesis for high throughput DSP applications , 1991, 28th ACM/IEEE Design Automation Conference.

[19]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[20]  Hugo De Man,et al.  A specification invariant technique for operation cost minimisation in flow-graphs , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[21]  Hugo De Man,et al.  High-level synthesis for real-time digital signal processing , 1993, The Kluwer international series in engineering and computer science.

[22]  H. De Man,et al.  Dataflow-driven Memory Allocation For Multi-dimensional Signal Processing Systems , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[23]  Jan M. Rabaey,et al.  DSP specification using the Silage language , 1990 .

[24]  E.A. Lee Programmable DSP architectures. II , 1989, IEEE ASSP Magazine.

[25]  Donald E. Thomas,et al.  Behavioral transformation for algorithmic level IC design , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[27]  Mario Barbacci,et al.  Instruction set processor specifications (ISPS): The notation and its applications , 1981, IEEE Transactions on Computers.

[28]  Vicki H. Allan,et al.  Global methods in the flow graph approach to retargetable microcode generation , 1984, MICRO 17.

[29]  Michael Goldsmith,et al.  Programming in occam 2 , 1985, Prentice Hall international series in computer science.

[30]  Miodrag Potkonjak,et al.  Optimizing resource utilization using transformations , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  John R. Ellis,et al.  Bulldog: A Compiler for VLIW Architectures , 1986 .

[32]  Alois Knoll,et al.  Generation of hardware machine models from instruction set descriptions , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[33]  Edward A. Lee,et al.  Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems , 2001, Int. J. Comput. Simul..

[34]  Edward A. Lee,et al.  A hardware-software codesign methodology for DSP applications , 1993, IEEE Design & Test of Computers.

[35]  Hugo De Man,et al.  Instruction set definition and instruction selection for ASIPs , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[36]  Hugo De Man,et al.  Data routing: a paradigm for efficient data-path synthesis and code generation , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[37]  Bill Lin,et al.  A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules , 1994, 31st Design Automation Conference.

[38]  Fadi J. Kurdahi,et al.  Partitioning by regularity extraction , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[39]  Hugo De Man,et al.  Memory and Data-Path Mapping for Image and Video Applications , 1993 .

[40]  C. Van Himbeeck The use of CDMA in European mobile satellite communication systems , 1994, ISSSTA 1994.

[41]  Ahmed Amine Jerraya,et al.  Interactive system-level partitioning with PARTIF , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[42]  Rudy Lauwereins,et al.  Static scheduling of multi-rate and cyclo-static DSP-applications , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[43]  Hugo De Man,et al.  A generalized state assignment theory for transformations on signal transition graphs , 1994, J. VLSI Signal Process..

[44]  H. De Man,et al.  User requirements for designing complex systems on silicon , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[45]  H.J. De Man,et al.  Automating High Level Control F'low Transformations For Dsp Memory Management , 1992, Workshop on VLSI Signal Processing.

[46]  B. Lin,et al.  Sizing of communication buffers for communicating signal processes , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[47]  Hugo De Man,et al.  Silicon Synthesis of a Flexible CDMA/QPSK Mobile Communication Modem , 1994 .

[48]  Pierre G. Paulin,et al.  DSP design tool requirements for embedded systems: A telecommunications industrial perspective , 1995, J. VLSI Signal Process..

[49]  Bill Lin,et al.  Synthesis Of Concurrent System Interface Modules With Automatic Protocol Conversion Generation , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[50]  Hugo De Man,et al.  Synthesis of High Throughput DSP ASICs Using Application Specific Datapaths , 1994 .

[51]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.