Wafer level test arrays with simple BIST to expedite process development for circuit reliability

Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.

[1]  K. Wu,et al.  Frequency dependence of NBTI in high-k/metal-gate technology , 2014, 2014 IEEE International Reliability Physics Symposium.

[2]  S. Deora,et al.  A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery , 2011, 2011 International Reliability Physics Symposium.

[3]  W. Wang,et al.  Delay effects and frequency dependence of NBTI with sub-microsecond measurements , 2015, 2015 IEEE International Reliability Physics Symposium.

[4]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[5]  S. Ramey,et al.  BTI recovery in 22nm tri-gate technology , 2014, 2014 IEEE International Reliability Physics Symposium.

[6]  T. Grasser,et al.  Hydrogen-related volatile defects as the possible cause for the recoverable component of NBTI , 2013, 2013 IEEE International Electron Devices Meeting.

[7]  S. Mahapatra,et al.  On the differences between ultra-fast NBTI measurements and Reaction-Diffusion theory , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[8]  B. Wagner,et al.  Process window and device variations evaluation using array-based characterization circuits , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).