Reconfigurable computing

Reconfigurable computing is a new and emerging field that makes use of programmable devices to construct "custom computing machinery". In this paper, we introduce the research area, present a classification of reconfigurable architectures, present various implementation options, and describe some of the open research problems related to reconfigurable computing.

[1]  Mark Shand,et al.  Programmable active memories: reconfigurable systems come of age , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[3]  Brad L. Hutchings,et al.  Design methodologies for partially reconfigured systems , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[4]  Michael J. Wirthlin,et al.  The Nano Processor: a low resource reconfigurable processor , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[5]  Chung-Kuan Cheng,et al.  Routability improvement using dynamic interconnect architecture , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Steven A. Guccione,et al.  Classification and Performance of Reconfigurable Architectures , 1995, FPL.

[7]  Brad L. Hutchings,et al.  Implementation Approaches for Reconfigurable Logic Applications , 1995, FPL.

[8]  Faustina Hwang,et al.  A Two-Stage Rearrangeable Broadcast Switching Network , 1985, IEEE Trans. Commun..

[9]  Jean Vuillemin,et al.  Programmable Active Memories: A Performance Assessment , 1992, Heinz Nixdorf Symposium.

[10]  Joseph Varghese,et al.  An efficient logic emulation system , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[11]  Scott Hauck,et al.  The roles of FPGAs in reprogrammable systems , 1998, Proc. IEEE.

[12]  Pierre Marchal,et al.  Field-programmable gate arrays , 1999, CACM.

[13]  Laurent Moll,et al.  High-Energy Physics on DECPeRLe-1 Programmable Active Memory , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[14]  Daniel P. Lopresti,et al.  SPLASH: A Reconfigurable Linear Logic Array , 1990, ICPP.

[15]  Duncan A. Buell,et al.  Splash 2 , 1992, SPAA.

[16]  Charles Clos,et al.  A study of non-blocking switching networks , 1953 .

[17]  A. Mullin,et al.  Mathematical Theory of Connecting Networks and Telephone Traffic. , 1966 .

[18]  Anant Agarwal,et al.  TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire™ Compilation , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[19]  Chung-Kuan Cheng,et al.  Multiple-level partitioning: an application to the very large-scale hardware simulator , 1991 .

[20]  Mark Shand,et al.  Fast implementations of RSA cryptography , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[21]  Abbas El Gamal,et al.  Two-dimensional stochastic model for interconnections in master-slice integrated circuits , 1981 .

[22]  Martine D. F. Schlag,et al.  On Routability Prediction for Field-Programmable Gate Arrays , 1993, 30th ACM/IEEE Design Automation Conference.

[23]  Anant Agarwal,et al.  Logic emulation with virtual wires , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Ian Page.  Constructing hardware-software systems from a single description , 1996, J. VLSI Signal Process..

[25]  Herman Schmit.  Incremental reconfiguration for pipelined applications , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[26]  S. Monaghan,et al.  Reconfigurable multi-bit processor for DSP applications in statistical physics , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[27]  Chingwei Yeh.  On the acceleration of flow-oriented circuit clustering , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Eduardo Sanchez,et al.  Spyder: a reconfigurable VLIW processor using FPGAs , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[29]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .

[30]  Chung-Kuan Cheng,et al.  Performance-Driven Partitioning Using a Replication Graph Approach , 1995, 32nd Design Automation Conference.

[31]  Jean Vuillemin,et al.  Introduction to programmable active memories , 1990 .

[32]  J. Davidson.  FPGA implementation of a reconfigurable microprocessor , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[33]  Richard Cole,et al.  On Edge Coloring Bipartite Graphs , 1980, SIAM J. Comput..

[34]  Martine D. F. Schlag,et al.  Architectural tradeoffs in field-programmable-device-based computing systems , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[35]  Dzung T. Hoang,et al.  Searching genetic databases on Splash 2 , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[36]  Eric Lemoine,et al.  Run time reconfiguration of FPGA for scanning genomic databases , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[37]  Shih-Chieh Chang,et al.  Layout Driven Logic Synthesis for FPGAs , 1994, 31st Design Automation Conference.

[38]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[39]  Chingwei Yeh,et al.  A probabilistic multicommodity-flow solution to circuit clustering problems , 1992, ICCAD.

[40]  B. Box.  Field programmable gate array based reconfigurable preprocessor , 1994, Proceedings of National Aerospace and Electronics Conference (NAECON'94).

[41]  Ernest S. Kuh,et al.  Performance-Oriented Fully Routable Dynamic Architecture for a Field , 1993 .

[42]  Manfred Glesner,et al.  A reconfigurable computer for embedded control applications , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[43]  S. Casselman.  Virtual computing and the Virtual Computer , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[44]  Tsuyoshi Isshiki,et al.  High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[45]  Dhiraj K. Pradhan,et al.  Fault-tolerant computing : theory and techniques , 1986 .

[46]  D.M. Lewis,et al.  A field programmable accelerator for compiled-code applications , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[47]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[48]  Brad L. Hutchings,et al.  A dynamic instruction set computer , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[49]  R. W. Taylor,et al.  A self-reconfiguring processor , 1993 .

[50]  Martine D. F. Schlag,et al.  BORG: A RECONFIGURABLE PROTOTYPING BOARD USING FIELD-PROGRAMMABLE GATE ARRAYS , 1991 .