Circuit and Methodology for Testing Small Delay Faults in the Clock Network
暂无分享,去创建一个
Shi-Yu Huang | Wu-Tung Cheng | Kun-Han Tsai | Shaofu Yang | Zhi-Yuan Wen | Shi-Yu Huang | Kun-Han Tsai | Wu-Tung Cheng | Shaofu Yang | Zhi-Yuan Wen
[1] Fangming Ye,et al. TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation , 2012, DAC Design Automation Conference 2012.
[2] Cecilia Metra,et al. Can clock faults be detected through functional test? , 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.
[3] Shi-Yu Huang,et al. Pulse-Vanishing Test for Interposers Wires in 2.5-D IC , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Giovanni De Micheli,et al. Effect of process variations in 3D global clock distribution networks , 2012, JETC.
[5] P.R. O'Brien,et al. Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[6] L. Arnaud,et al. Resistance increase due to electromigration induced depletion under TSV , 2011, 2011 International Reliability Physics Symposium.
[7] Suk-kyu Ryu,et al. Thermal stress induced delamination of through silicon vias in 3-D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
[8] L. Arnaud,et al. Electromigration behavior of 3D-IC TSV interconnects , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[9] Shi-Yu Huang,et al. Small delay testing for TSVs in 3-D ICs , 2012, DAC Design Automation Conference 2012.
[10] Hiroshi Takahashi,et al. Fault simulation and test generation for clock delay faults , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).
[11] Cecilia Metra,et al. Novel Approach to Clock Fault Testing for High Performance Microprocessors , 2007, 25th IEEE VLSI Test Symposium (VTS'07).
[12] TingTing Hwang,et al. Clock tree synthesis with methodology of re-use in 3D IC , 2012, DAC '12.
[13] Shi-Yu Huang,et al. On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs , 2014, 2014 IEEE 23rd Asian Test Symposium.
[14] B. Banijamali,et al. Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.
[15] Shi-Yu Huang,et al. Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Yiyu Shi,et al. Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] Fangming Ye,et al. TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).
[18] Katherine Shu-Min Li,et al. Synthesis of 3D clock tree with pre-bond testability , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).
[19] Shi-Yu Huang,et al. At-speed BIST for interposer wires supporting on-the-spot diagnosis , 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).
[20] Cheng-Wen Wu,et al. 3D-IC interconnect test, diagnosis, and repair , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).
[21] N.A. Kurd,et al. Multi-GHz clocking scheme for Intel(R) Pentium(R) 4 microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[22] Eby G. Friedman,et al. Clock Distribution Networks in 3-D Integrated Systems , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[23] Cecilia Metra,et al. New Design for Testability Approach for Clock Fault Testing , 2012, IEEE Transactions on Computers.