Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study

This paper investigates the state of the current high-level synthesis (HLS) tools by using Xilinx Vivado HLS for designing a cryptographic module based on Advanced Encryption Standard. The obtained results are compared with the results for the hand-written Register-Transfer Level (RTL) VHDL code to determine the suitability of the HLS-based approach for implementing cryptographic algorithms in hardware. Our study has shown that the RTL-based approach still outperforms the HLS-based approach due to the flexibility in designing a control unit, which affects the throughput of the circuit. Nevertheless, the HLS-based approach can successfully compete with the RTL-based approach in terms of area and maximum clock frequency.

[1]  Flavius Gruian,et al.  VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture , 2008, SAC '08.

[2]  Albert Koelmans,et al.  Dynamic global security-aware synthesis using SystemC , 2007, IET Comput. Digit. Tech..

[3]  Jason Cong,et al.  High-Level Synthesis for FPGAs: From Prototyping to Deployment , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Morris J. Dworkin,et al.  Recommendation for Block Cipher Modes of Operation: The CCM Mode for Authentication and Confidentiality [including updates through 7/20/2007] , 2004 .

[5]  Gang Quan,et al.  High-level synthesis for large bit-width multipliers on FPGAs: a case study , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[6]  Yun Liang,et al.  A study of high-level synthesis: Promises and challenges , 2011, 2011 9th IEEE International Conference on ASIC.

[7]  Sandeep K. Shukla,et al.  Hardware Coprocessor Synthesis from an ANSI C Specification , 2009, IEEE Design & Test of Computers.

[8]  Sorin A. Huss,et al.  Rapid prototyping for hardware accelerated elliptic curve public-key cryptosystems , 2001, Proceedings 12th International Workshop on Rapid System Prototyping. RSP 2001.

[9]  Satoshi Obana,et al.  Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology , 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

[10]  Kris Gaj,et al.  ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[11]  Kris Gaj,et al.  Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs , 2010, CHES.

[12]  Russ Housley,et al.  Using Advanced Encryption Standard (AES) Counter Mode With IPsec Encapsulating Security Payload (ESP) , 2004, RFC.

[13]  Gary Smith,et al.  High-Level Synthesis: Past, Present, and Future , 2009, IEEE Design & Test of Computers.

[14]  High-Level Synthesis Tools for Xilinx FPGAs , 2010 .

[15]  Yu Mao,et al.  Using Advanced Encryption Standard Counter Mode (AES-CTR) with the Internet Key Exchange version 02 (IKEv2) Protocol , 2010, RFC.

[16]  Yun Liang,et al.  High-Level Synthesis: Productivity, Performance, and Software Constraints , 2012, J. Electr. Comput. Eng..

[17]  Hiroyuki Tomiyama,et al.  CHStone: A benchmark program suite for practical C-based high-level synthesis , 2008, 2008 IEEE International Symposium on Circuits and Systems.