Synthesis of high-speed A/D converter architectures with flexible functional simulation capabilities

A CAD tool for high-level synthesis of high-speed analog-to-digital (A/D) converter architectures is described, which includes a flexible functional simulation capability taking into account the most relevant electrical parameters. By using the flash quantizer and the charge-redistribution multiplying digital-to-analog converter (MDAC) blocks as the only mixed-signal functional primitives, this tool is capable of synthesizing multiple architectures, including the flash, subranging, two-step flash and pipelined AID converters. The tool analyzes and determines the required high level building block specifications, based on functional models which accurately describe the dominant poles of the electrical behavior of the lowest-level building-blocks, namely arrays of switches, arrays of capacitors, resistor strings, operational amplifiers and comparators. A functional simulation based on such models is included.<<ETX>>

[1]  Alberto L. Sangiovanni-Vincentelli,et al.  CADICS-cyclic analog-to-digital converter synthesis , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[2]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .

[3]  A. Dingwall,et al.  An 8MHz 8b CMOS subranging ADC , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  T. Tsukada,et al.  CMOS 8b 25MHz flash ADC , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  J. Doernberg,et al.  A 10-bit 5-Msample/s CMOS two-step flash ADC , 1989 .

[6]  A.G.F. Dingwall,et al.  Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter , 1979, IEEE Journal of Solid-State Circuits.

[7]  Jose E. Franca,et al.  Framework for architecture synthesis of data conversion systems employing binary-weighted capacitor arrays , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[8]  Guido Torelli,et al.  A novel approach for high-frequency pipelined A/D conversion , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[9]  Paul R. Gray,et al.  A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS , 1991 .

[10]  M. S. Tawfik,et al.  HiFADiCC: a prototype framework of a highly flexible analog to digital converters silicon compiler , 1990, IEEE International Symposium on Circuits and Systems.

[11]  Donald A. Kerth,et al.  A 12-bit, 1-MHz, two-step flash ADC , 1989 .