Object oriented lisp implementation of the CHEOPS VLSI floor planning and routing system

This paper presents the architecture and capabilities of the CHEOPS Floor Planning and Routing System for macrocell VLSI design, which was implemented in Le-Lisp (@ from INRIA) using Object Oriented Programming. CHEOPS is a highly interactive system providing an integrated set of facilities allowing VLSI designers to cover all steps from initial floorplan evaluation down to final chip composition and detailed routing. It is based on a memory data structure that uniformly models topology and connectivity through all floorplan refinement steps.

[1]  J.-M. Servant,et al.  Silicon compiler generates fast multipliers embedded in data path , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[2]  Ernest S. Kuh,et al.  A Dynamic and Efficient Representation of Building-Block Layout , 1987, 24th ACM/IEEE Design Automation Conference.

[3]  James Cherry.  CAD Programming in an Object Oriented Programming Environment , 1987 .

[4]  Rémy Escassut.  Tracé automatique hiérarchisé d'interconnexions de blocs fonctionnels de circuits intégrés V. L. S. I , 1988 .

[5]  P. Groenveld,et al.  On Global Wire Ordering for Macro-Cell Routing , 1989, DAC.

[6]  Timothy J. Barnes.  SKILL: A CAD system extension language , 1991, DAC '90.

[7]  Takeshi Yoshimura.  An Efficient Channel Router , 1984, 21st Design Automation Conference Proceedings.

[8]  P. Groeneveld,et al.  On Global Wire Ordering for Macro-Cell Routing , 1989, 26th ACM/IEEE Design Automation Conference.

[9]  Ernest S. Kuh,et al.  Nutcracker: An Efficient and Intelligent Channel Spacer , 1987, 24th ACM/IEEE Design Automation Conference.