Low-frequency VLSI architecture with a binary data buffer for H.264 CABAC

In the H.264 encoding process, CABAC is a significant issue in real-time implementation, because of the difficulty involved in its parallel processing. Moreover, the number of symbols of each macroblock varies greatly. Therefore, a high clock frequency is needed to satisfy the required peak performance. In the preset paper, we proposed efficient VLSI architecture of H.264 CABAC. In the proposed architecture, by storing binary data into frame memory, the required peak performance can be reduced to 1/20, and real-time execution of HD video sequences at low clock frequencies, such as 100 ㎒, can be achieved.