This paper covers the state parallel Viterbi decoder soft IP (intellectual property) and its applications. We have designed a reusable soft IP of parallel structure Viterbi decoder. It can automatically generate synthesizable Verilog-HDL source codes of the Viterbi decoder and convolutional encoder, synthesis scripts and a simple testbench with user defined parameters. The Viterbi decoder core generated from the IP has state-parallel structure with path memory of register exchange type. It is applied successfully to the FEC (forward error correction) of the wideband direct sequence CDMA (code division multiple access) satellite communication system and the TCM (trellis coded modulation) demodulator of the cable modem system.
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