A Four-Step Incremental ADC Based on Double Extended Binary Counting With Capacitive DAC

This brief proposes a discrete-time four-step reconfigurable incremental ADC (IADC) which consists of a first-step SAR conversion, a second-step IADC operation, and double extended binary counting (EBC). While coarse conversion with the 8b SAR ADC is preceded, instead of 8b DAC, 7b capacitive DAC based integrator operation in the IADC becomes available to reduce the chip area and power consumption of amplifier. Additional resolution is achieved by performing the EBC twice, where its conversion time is reduced by using the binary operation with a 7b capacitive DAC. The IADC and the EBC are reconfigured to utilize the same sub-blocks of one amplifier and one comparator, thus reducing silicon area and obtaining high linearity. A prototype ADC is fabricated in a 180-nm CMOS process, and it achieves 179.7 dB FoM and consumes 176 $\mu \text{W}$ .