Unique ESD failure mechanisms during negative to Vcc HBM tests

Abstract HBM ESD tests on two types of 0.6  μ m DRAM devices showed that internal circuit or output driver failures would occur after the input or I/O pins were ESD stressed negative with respect to Vcc at ground. These failures occurred at lower than expected ESD stress voltages due to power-up circuit interactions that either turned-on unique internal parasitic ESD current paths or disrupted the normal operation of the output pin’s ESD protection circuit. ESD analysis found there exists a set of power-up sensitive circuits and if placed near a Vcc bond pad can result in low voltage ESD failures.

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