Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

An electrostatic discharge (ESD) evaluation of a silicided 0.25 μm complementary metal-oxide-semiconductor (CMOS) technology is carried out by HBM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.

[1]  R. Byron Bird,et al.  Squeezing Flow between Parallel Disks. I. Theoretical Analysis , 1974 .

[2]  W. H. Leong,et al.  Underfill flow as viscous flow between parallel plates driven by capillary action , 1995, Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'.

[3]  Sejin Han,et al.  Experimental and analytical study on the flow of encapsulant during underfill encapsulation of flip-chips , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.

[4]  D.F. Baldwin,et al.  Advanced encapsulation processing for low cost electronics assembly-a cost analysis , 1997, Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces.

[5]  D. Baldwin,et al.  Manufacturability of Underfill Processing for Low Cost Flip Chip , 1997, Structural Analysis in Microelectronics and Fiber Optics.

[6]  D. R. Gamota,et al.  The development of reflowable materials systems to integrate the reflow and underfill dispensing processes for DCA/FCOB assembly , 1997 .

[7]  Daniel F. Baldwin,et al.  Compression flow modeling of underfill encapsulants for low cost flip chip assembly , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).