Stimuli Generation for Functional Hardware Verification with Constraint Programming

We survey the application of constraint programming techniques for stimuli generation in functional hardware verification, which can be considered the largest and most important industrial application of constraint programming. We provide a thorough introduction to the application domain, aimed at people unfamiliar with this area. We show the sources of constraints and the unique aspects of the constraint satisfaction problems (CSPs) arising in this field. We then present CSP models of a wide variety of stimuli generation problems, as well as the state of the art techniques used to solve them. We also discuss the current challenges in this area, and the prospects of solving them by advancing constraint programming technology beyond the state of the art.

[1]  Yehuda Naveh,et al.  Constraint-Based Random Stimuli Generation for Hardware Verification , 2006, AI Mag..

[2]  Avi Ziv,et al.  Using Linear Programming Techniques for Scheduling-Based Random Test-Case Generation , 2006, Haifa Verification Conference.

[3]  Allon Adir,et al.  VLIW - a case study of parallelism verification , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[4]  Thomas Kropf,et al.  Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.

[5]  Koushik Sen,et al.  DART: directed automated random testing , 2005, PLDI '05.

[6]  Wolfgang Roesner,et al.  Comprehensive Functional Verification: The Complete Industry Cycle , 2005 .

[7]  Yue Yang,et al.  QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings , 2004, CAV.

[8]  Michael Veksler,et al.  Assumption-Based Pruning in Conditional CSP , 2005, CP.

[9]  Avi Ziv,et al.  Using a constraint satisfaction formulation and solution techniques for random test program generation , 2002, IBM Syst. J..

[10]  A. K. Chandra,et al.  Constraint solving for test case generation: a technique for high-level design verification , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[11]  B. Gutkovich,et al.  CP with Architectural State Lookup for Functional Test Generation , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

[12]  Luciano Lavagno,et al.  Electronic Design Automation for Integrated Circuits Handbook , 2006 .

[13]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[14]  Rina Dechter,et al.  Generating random solutions for constraint satisfaction problems , 2002, AAAI/IAAI.

[15]  Heinrich Meyr,et al.  LISA—machine description language for cycle-accurate models of programmable DSP architectures , 1999, DAC '99.

[16]  Phillip B. Gibbons,et al.  The complexity of sequential consistency , 1992, [1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing.

[17]  Yue Yang,et al.  Nemos: a framework for axiomatic and executable specifications of memory consistency models , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[18]  Anna Moss,et al.  Constraint Patterns and Search Procedures for CP-Based Random Test Generation , 2007, Haifa Verification Conference.

[19]  Alan Borning,et al.  Constraint hierarchies , 1992 .

[20]  Yoav Hollander,et al.  The e language: a fresh separation of concerns , 2001, Proceedings Technology of Object-Oriented Languages and Systems. TOOLS 38.

[21]  Eugene C. Freuder.  In pursuit of the holy grail , 1996, CSUR.

[22]  Heinrich Meyr,et al.  LISA-machine description language and generic machine model for HW/SW co-design , 1996, VLSI Signal Processing, IX.

[23]  Allon Adir,et al.  Piparazzi: a test program generator for micro-architecture flow verification , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

[24]  Alessandro Armando,et al.  Bounded model checking of software using SMT solvers instead of SAT solvers , 2006, International Journal on Software Tools for Technology Transfer.

[25]  Edmund M. Clarke,et al.  Model Checking , 1999, Handbook of Automated Reasoning.

[26]  L. Fournier,et al.  Constraint satisfaction for test program generation , 1995, Proceedings International Phoenix Conference on Computers and Communications.

[27]  Thomas Ellman,et al.  Abstraction via Approximate Symmetry , 1993, IJCAI.

[28]  Yehuda Naveh,et al.  Preprocessing Expression-Based Constraint Satisfaction Problems for Stochastic Local Search , 2007, CPAIOR.

[29]  Sigal Asaf,et al.  FPgen - a test generation framework for datapath floating-point verification , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

[30]  Sarita V. Adve,et al.  Shared Memory Consistency Models: A Tutorial , 1996, Computer.

[31]  M.K. Ganai,et al.  Accelerating High-level Bounded Model Checking , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[32]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[33]  Allon Adir,et al.  Genesys-Pro: innovations in test program generation for functional processor verification , 2004, IEEE Design & Test of Computers.

[34]  Helmut Simonis,et al.  Test Generation using the Constraint Logic Programming Language CHIP , 1989, International Conference on Logic Programming.

[35]  Jian Zhang,et al.  A Constraint Solver and Its Application to Path Feasibility Analysis , 2001, Int. J. Softw. Eng. Knowl. Eng..

[36]  Aharon Aharon,et al.  Model Based Test Generation for Processor Verification , 1994, IAAI.

[37]  Pascal Van Hentenryck,et al.  Constraint Satisfaction Using Constraint Logic Programming , 1992, Artif. Intell..

[38]  Yehuda Naveh.  Stochastic solver for constraint satisfaction problems with learning of high-level characteristics of the problem topography , 2004 .

[39]  Willem-Jan van Hoeve,et al.  Over-Constrained Problems , 2011 .

[40]  Yehuda Naveh,et al.  X-Gen: a random test-case generator for systems and SoCs , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

[41]  Mikko H. Lipasti,et al.  The complexity of verifying memory coherence and consistency , 2005, IEEE Transactions on Parallel and Distributed Systems.

[42]  Yehuda Naveh.  Guiding Stochastic Search by Dynamic Learning of the Problem Topography , 2008, CPAIOR.

[43]  Allon Adir,et al.  A Framework for the Validation of Processor Architecture Compliance , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[44]  Yossi Lichtenstein,et al.  Industrial experience with test generation languages gar processor verification , 2004, Proceedings. 41st Design Automation Conference, 2004..

[45]  Mark A. Check,et al.  IBM System z10 I/O subsystem , 2009, IBM J. Res. Dev..

[46]  Allon Adir,et al.  Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture , 2003, IEEE Trans. Parallel Distributed Syst..

[47]  Mahesh A. Iyer,et al.  Race a word-level atpg-based constraints solver system for smart random simulation , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[48]  Aaron Tsai,et al.  Design and microarchitecture of the IBM system z10 microprocessor , 2009 .

[49]  Brian Falkenhainer,et al.  Dynamic Constraint Satisfaction Problems , 1990, AAAI.

[50]  Allon Adir,et al.  Addressing Test Generation Challenges for Configurable Processor Verification , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

[51]  Allon Adir,et al.  DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.