Automating timed specification transparency for human designer validation of real-time discrete-event control requirements

In supervisory control of discrete-event systems, prescribing formal specifications is a non-trivial task that depends on the intuition and cognitive understanding of the designer. A human designer has no assurance if a prescribed specification is as intended, making it necessary to manually validate the specification, i.e., check whether the specification does indeed prescribe the intended requirement. This uncertainty in specification is compounded in the case of timed discrete-event systems (TDES's), where real-timing behavior also needs to be correctly specified. The fundamental control theory for TDES's requires a specification to be formalized as a timed transition graph (TTG), prescribing a timed regulation of logical behavior that restricts a TDES to some timed execution sequences. To help validate the specification, human designers need an algorithm that can automatically remodel the TTG specification, to highlight sequences essential for comprehending the specification's timed restrictions while hiding irrelevant information. By `hiding' in self-loops the associated events of all transitions deemed irrelevant to the specification, we can obtain a more comprehensible TTG, formalized by what we call a transparent TTG specification. In this paper, we propose a polynomial-time algorithm to compute TTG specifications of clear transparency.

[1]  W. Wonham,et al.  Supervisory control of timed discrete-event systems , 1994, IEEE Trans. Autom. Control..

[2]  Viktor Schuppan,et al.  RATSY - A New Requirements Analysis Tool with Synthesis , 2010, CAV.

[3]  Marc Geilen,et al.  Software/Hardware Engineering with the Parallel Object-Oriented Specification Language , 2007, 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007).

[4]  W. M. Wonham,et al.  Supervisor Reduction for Discrete-Event Systems , 2004, Discret. Event Dyn. Syst..

[5]  Shengbing Jiang,et al.  2080 SHENGBING JIANG AND RATNESH KUMAR , 2006 .

[6]  A. Saadatpoor,et al.  Supervisor State Size Reduction for Timed Discrete-Event Systems , 2007, 2007 American Control Conference.

[7]  Kiam Tian Seow,et al.  On the transparency of automata as discrete-event control specifications , 2010, 2010 IEEE International Conference on Robotics and Automation.

[8]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[9]  Christos G. Cassandras,et al.  Introduction to Discrete Event Systems , 1999, The Kluwer International Series on Discrete Event Dynamic Systems.

[10]  P. Ramadge,et al.  Supervisory control of a class of discrete event processes , 1987 .

[11]  J.E.R. Cury,et al.  Design of discrete-event systems using templates , 2008, 2008 American Control Conference.

[12]  Kiam Tian Seow Integrating Temporal Logic as a State-Based Specification Language for Discrete-Event Control Design in Finite Automata , 2007, IEEE Transactions on Automation Science and Engineering.

[13]  Ron Koymans,et al.  Specifying real-time properties with metric temporal logic , 1990, Real-Time Systems.

[14]  Jonathan S. Ostroff,et al.  Temporal logic for real-time systems , 1989 .