论文信息 - Domino logic with dynamic body biased keeper

Domino logic with dynamic body biased keeper

A dynamic body biased keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The proposed circuit technique is applied to wide fan-in domino OR gates. With the proposed dynamic body biased keeper circuit technique, circuit evaluation speed is increased by up to 66% while reducing power dissipation by 43% as compared to standard domino logic circuits.

V. Kursun | E.G. Friedman

[1] Mohamed I. Elmasry,et al. High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[2] Eby G. Friedman,et al. Low swing dual threshold voltage domino logic , 2002, GLSVLSI '02.

[3] A. Alvandpour,et al. A leakage-tolerant multi-phase keeper for wide domino circuits , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).