Neural algorithms for cell placement in VLSI design

The authors present a modified Tank and Hopfield neural network for solving the problem of cell placement in integrated circuits, a constrained optimization problem that is NP-complete. The neural network is composed of two mutually interconnected subcircuits. One determines the configuration of cells on the plane for which the bounding box area and connections reach a minimum, whereas the other satisfies the nonoverlapping constraints among cells. The global-local minima issue is addressed and solved in two steps. First, the initial X-Y condition from which the system is permitted to evolve toward minima is determined by solving a relaxed problem that has global minima located in regions of the state space close to those of the original problem. Second, the initial orientation of blocks is determined by a more detailed analysis of connectivity requirements. The proposed neural network paradigm has been simulated and tested for small and medium-sized integrated circuits.<<ETX>>

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