Customised soft processor design: a compromise between architecture description languages and parameterisable processors

Processor customisation is an effective technique to enhance performance across an application domain. In this study, the authors present a new customised soft processor development environment called polytechnique customised soft processor (PolyCuSP), which bridges the gap between architecture description languages (ADLs) and extensible soft processors. The main objective of this environment is to facilitate rapid design space exploration while preserving a wide range of customisation flexibility. For this purpose, PolyCuSP offers full flexibility in instruction-set description, while limiting the datapath customisation to a predefined set of tunable microarchitectural parameters. The environment avoids extensive datapath description that is unnecessary for usual microarchitectural customisation techniques in order to simplify the development process. A new XML-based description format is introduced for instruction-set modelling. Experimental results evaluate and compare the design and customisation complexities offered by PolyCuSP with competitive approaches. Results demonstrate the efficiency of applying customisation techniques in the proposed environment. For the Sobel edge detection algorithm, the results show that microarchitectural tuning and instruction-set architecture customisation improve the performance-per-cost ratio by an average of 44 and 27%, respectively. Furthermore, in a case study of a tone-mapping algorithm, PolyCuSP achieves an average improvement of 38% in performance-per-cost ratio over an ADL-based design applying the same customisations.

[1]  Jonathan Rose,et al.  Application-specific customization of soft processor microarchitecture , 2006, FPGA '06.

[2]  James C. Hoe,et al.  Automatic Pipelining From Transactional Datapath Specifications , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Wayne Luk,et al.  CUSTARD - a customisable threaded FPGA soft processor and tools , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[4]  Prabhat Mishra,et al.  Architecture description languages for programmable embedded systems , 2005 .

[5]  Jonathan Rose,et al.  Exploration and Customization of FPGA-Based Soft Processors , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Hisham El-Shishiny,et al.  High-quality HDR rendering technologies for emerging applications , 2010, IBM J. Res. Dev..

[7]  Nikil D. Dutt,et al.  Behavioral array mapping into multiport memories targeting low power , 1997, Proceedings Tenth International Conference on VLSI Design.

[8]  Ricardo E. Gonzalez,et al.  Xtensa: A Configurable and Extensible Processor , 2000, IEEE Micro.

[9]  Kingshuk Karuri,et al.  A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) , 2009, SAMOS.

[10]  Mohammed A. S. Khalid,et al.  SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays , 2009, IET Comput. Digit. Tech..

[11]  J. Kairus,et al.  Bridging the gap between future software and hardware engineers: a case study using the Nios softcore processor , 2003, 33rd Annual Frontiers in Education, 2003. FIE 2003..

[12]  Patrick Akl,et al.  Datapath and ISA Customization for Soft VLIW Processors , 2006, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006).

[13]  Anshul Kumar,et al.  ASIP design methodologies: survey and issues , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[14]  Mark Horowitz,et al.  Using a configurable processor generator for computer architecture prototyping , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[15]  Yoshinori Takeuchi,et al.  PEAS-III: an ASIP design environment , 2000, Proceedings 2000 International Conference on Computer Design.

[16]  Rainer Leupers,et al.  LISA: A Uniform ADL for Embedded Processor Modeling, Implementation, and Software Toolsuite Generation , 2008 .

[17]  Yvon Savaria,et al.  Customized embedded processor design for global photographic tone mapping , 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

[18]  E. Reinhard Photographic Tone Reproduction for Digital Images , 2002 .

[19]  Young-Su Kwon,et al.  MetaCore: an application specific DSP development system , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).