A General S-Domain Hierarchical Network Reduction Algorithm
暂无分享,去创建一个
[1] Lawrence T. Pileggi,et al. PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.
[2] Mattan Kamon,et al. Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures , 1996 .
[3] Chi-Tsong Chen,et al. Linear System Theory and Design , 1995 .
[4] N. P. van der Meijs,et al. Including higher-order moments of RC interconnections in layout-to-circuit extraction , 1996, Proceedings ED&TC European Design and Test Conference.
[5] Chung-Kuan Cheng,et al. Hurwitz stable reduced order modeling for RLC interconnect trees , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[6] Sheldon X.-D. Tan,et al. Hurwitz stable model reduction for non-tree structured RLCK circuits [IC interconnect applications] , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..
[7] Ronald A. Rohrer,et al. Electronic Circuit and System Simulation Methods , 1994 .
[8] M. M. Hassoun,et al. A hierarchical network approach to symbolic analysis of large-scale networks , 1995 .
[9] Lawrence T. Pileggi,et al. Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Sheldon X.-D. Tan,et al. Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Roland W. Freund,et al. Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.
[12] Jacob K. White,et al. A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits , 1996, ICCAD 1996.
[13] John Lillis,et al. Interconnect Analysis and Synthesis , 1999 .
[14] Yehea I. Ismail,et al. DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[15] Sheldon X.-D. Tan,et al. Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[16] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[17] Jason Cong,et al. Performance optimization of VLSI interconnect layout , 1996, Integr..
[18] Chung-Kuan Cheng,et al. RCLK-VJ network reduction with Hurwitz polynomial approximation , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..
[19] Roland W. Freund,et al. Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm , 1996, ICCAD 1996.
[20] Rob A. Rutenbar,et al. Canonical Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams , 2002 .
[21] Sheldon X.-D. Tan,et al. Balanced multi-level multi-way partitioning of large analog circuits for hierarchical symbolic analysis , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).
[22] Georges Gielen,et al. Hierarchical Symbolic Analysis of Large Analog Circuits , 1998 .
[23] Roland W. Freund,et al. Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm , 1995, 32nd Design Automation Conference.