A General S-Domain Hierarchical Network Reduction Algorithm

This paper presents an efficient method to reduce complexities ofa linear network in s-domain. The new method works on circuitmatrices directly and reduces the circuit complexities by eliminatingsubcircuits in a hierarchical way. The resulting admittancesin the reduced networks are kept as rational functions of s withreduced order. Some theoretical results are characterized for thepresence of common factors coming from the suppression of subcircuits.A novel common factor removal (de-cancellation) strategybased on a graph-based hierarchical subcircuit reduction processis proposed. The resulting reduction algorithm is applicableto any linear circuits in s-domain. The stability of the reduced systemis enforced by applying the Hurwitz polynomial approximation.The reduced systems can be used for fast s-domain analysisand for time domain waveform evaluation. Experimental resultson both linear analog circuits and RLC circuits, and comparisonwith SPICE in s-domain analysis are also provided.

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