Power optimization for H.263/MPEG-4 VLSI video coding

In this paper the design of a VLSI architecture for H.263/MPEG-4 low-power video coding is addressed. Coder high-level modeling and relevant software profiling determines a hardware-software system partitioning based on a RISC engine enhanced by dedicated hardware processing. To reduce the system power consumption two main strategies have been pursued. The first consists in the design of a low-power high efficiency hardware co-processor for motion estimation. It is based on a fast predictive algorithm which, exploiting the correlation of video motion field, attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decrease algorithm complexity with proper low-power VLSI design techniques the motion estimation power consumption can be reduced down to 2 mW. Secondly, after a trade-off analysis in terms of memory area complexity and memory and system bus power consumption, a proper buffer hierarchy configuration have been implemented for the DMA-based hardware-software interface. With reference to the trivial case with no buffering a memory and bus power reduction of 78% and 90% respectively can be achieved. Finally, performance measurements on a FPGA-based emulation platform validate our analysis. Key-Words: Image coding, Motion Estimation, Low-Power, VLSI Architecture, Hardware-Software co-design.